Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

Preview PDF HTML

ST16C552AIJ68 Scheda tecnica(PDF) 16 Page - Exar Corporation

Il numero della parte ST16C552AIJ68
Spiegazioni elettronici  DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT
PDF  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  EXAR [Exar Corporation]
Homepage  http://www.exar.com
Logo EXAR - Exar Corporation

ST16C552AIJ68 Scheda tecnica(HTML) 16 Page - Exar Corporation

Back Button ST16C552AIJ68 Datasheet HTML 12Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 13Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 14Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 15Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 16Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 17Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 18Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 19Page - Exar Corporation ST16C552AIJ68 Datasheet HTML 20Page - Exar Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 39 page
background image
16
ST16C552/552A
Rev. 3.40
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The
assigned bit functions are more fully defined in the following paragraphs.
Table 7, ST16C552/552A INTERNAL REGISTERS
A2 A1 A0
Register
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
[Default]
Note 5*
General Register Set: Note 1*
0
0
0
RHR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
0
THR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
IER [00]
0
0
En
0
Modem
Receive
Transmit
Receive
Pwr
Status
Line
Holding
Holding
down
Interrupt
Status
Register
Register
mode
interrupt
interrupt
0
1
0
FCR [00]
RCVR
RCVR
0
0
DMA
XMIT
RCVR
FIFO
trigger
trigger
mode
FIFO
FIFO
enable
(MSB)
(LSB)
select
reset
reset
0
1
0
ISR [01]
FIFO’s
FIFO’s
0
0
INT
INT
INT
INT
enabled
enabled
priority
priority
priority
status
bit-2
bit-1
bit-0
0
1
1
LCR [00]
divisor
set
set
even
parity
stop
word
word
latch
break
parity
parity
enable
bits
length
length
enable
bit-1
bit-0
1
0
0
MCR [00]
Pwr
0
0
loop
INT A/B
[X]
-RTS
-DTR
down
back
enable
1
0
1
LSR [60]
FIFO
THR &
THR.
break
framing
parity
overrun
receive
data
TSR
empty
interrupt
error
error
error
data
error
empty
ready
1
1
0
MSR [X0]
CD
RI
DSR
CTS
delta
delta
delta
delta
-CD
-RI
-DSR
-CTS
1
1
1
SPR [FF]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
Special Register Set: Note *2
0
0
0
DLL [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
0
0
1
DLM [XX]
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com