OPA820-HT

www.ti.com

SBOS587

– DECEMBER 2011

Thermal Analysis

The OPA820 will not require heatsinking or airflow in most applications. Maximum desired junction temperature

would set the maximum allowed internal power dissipation as described below. In no case should the maximum

junction temperature be allowed to exceed 210

°C.

Quiescent power is simply the specified no-load supply current times the total supply voltage across the part.

PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a

maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies).

Note that it is the power in the output stage and not in the load that determines internal power dissipation.

Board Layout

Achieving optimum performance with a high-frequency amplifier such as the OPA820 requires careful attention to

board layout parasitics and external component types. Recommendations that will optimize performance include:

a. Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on

the output and inverting input pins can cause instability: on the noninverting input, it can react with the source

impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the

signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground

and power planes should be unbroken elsewhere on the board.

b. Minimize the distance (

< 0.25") from the power-supply pins to high-frequency 0.1-μF decoupling

capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the

signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the

decoupling capacitors. The power-supply connections should always be decoupled with these capacitors.

Larger (2.2-

μF to 6.8-μF) decoupling capacitors, effective at lower frequency, should also be used on the

main supply pins. These may be placed somewhat farther from the device and may be shared among

several devices in the same area of the PC board.

c. Careful selection and placement of external components will preserve the high-frequency

performance of the OPA820. Resistors should be a very low reactance type. Surface-mount resistors work

best and allow a tighter overall layout. Metal-film and carbon composition, axially leaded resistors can also

provide good high-frequency performance. Again, keep their leads and PC board trace length as short as

possible. Never use wire-wound type resistors in a high-frequency application. Since the output pin and

inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series

output resistor, if any, as close as possible to the output pin. Other network components, such as

noninverting input termination resistors, should also be placed close to the package. Where double-side

component mounting is allowed, place the feedback resistor directly under the package on the other side of

the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the

external resistors, excessively high resistor values can create significant time constants that can degrade

performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the

resistor. For resistor values

> 1.5 kΩ, this parasitic capacitance can add a pole and/or a zero below 500 MHz

that can effect circuit operation. Keep resistor values as low as possible consistent with load-driving

Ω. Using this setting will automatically keep the resistor noise terms low, and minimize the effect of their

parasitic capacitance.

d. Connections to other wideband devices on the board may be made with short direct traces or

through onboard transmission lines. For short connections, consider the trace and the input to the next

device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably

margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line

is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques

(consult an ECL design handbook for microstrip and stripline layout techniques). A 50-

Ω environment is

normally not necessary onboard, and in fact, a higher impedance environment will improve distortion as

shown in the distortion versus load plots. With a characteristic board trace impedance defined based on

Copyright

© 2011, Texas Instruments Incorporated

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Product Folder Link(s): OPA820-HT