AS4DDR232M72APBG datasheet(13/28 Pages) MICROSS

13 / 28 page

iPEM

2.4 Gb SDRAM-DDR2

AS4DDR232M72APBG

Rev. 1.1 12/12

Micross Components reserves the right to change products or specifications without notice.

POSTED CAS ADDITIVE LATENCY (AL)

Posted CAS additive latency (AL) is supported to make the

commandanddatabusefficientforsustainablebandwidths

in DDR2 SDRAM. Bits E3–E5 define the value ofAL, as

shown in Figure 7. Bits E3–E5 allow the user to program the

DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, or 4 clocks.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE

command to be issued prior to tRCD (MIN) with the requirement

that AL d” tRCD (MIN). A typical application using this feature

would set AL = tRCD (MIN) - 1x tCK. The READ or WRITE

command is held for the time of the AL before it is issued internally

to the DDR2 SDRAM device. RL is controlled by the sum of AL

and CL; RL = AL+CL. Write latency (WL) is equal to RL minus

one clock; WL = AL + CL - 1 x tCK.

FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION

POSTED CAS ADDITIVE LATENCY (AL)

Posted CAS additive latency (AL) is supported to make

the command and data bus efficient for sustainable

bandwidths in DDR2 SDRAM. Bits E3–E5 deﬁne the value

of AL, as shown in Figure 7. Bits E3–E5 allow the user

to program the DDR2 SDRAM with an inverse AL of 0, 1,

2, 3, or 4 clocks. Reserved states should not be used as

unknown operation or incompatibility with future versions

may result.

In this operation, the DDR2 SDRAM allows a READ or

WRITE command to be issued prior to tRCD (MIN) with

the requirement that AL ≤ tRCD (MIN). A typical application

using this feature would set AL = tRCD (MIN) - 1x tCK. The

READ or WRITE command is held for the time of the AL

before it is issued internally to the DDR2 SDRAM device.

RL is controlled by the sum of AL and CL; RL = AL+CL.

Write latency (WL) is equal to RL minus one clock; WL =

AL + CL - 1 x tCK.

FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION

BA0

BA1

A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0

Address Bus

ister (Ex)

7 6

5 4 3

1 0

Mode Register Definition

EMR2

01 01

01 01 01 01 01 01 01 01 01 01 01

use if T

Extended Mode

Reg

Mo de Register (MR)

Extended Mo de Register (EMR)

Extended Mo de Register (EMR2)

Extended Mo de Register (EMR3)

M15 M14

High Temperature Self Refresh rate enable

Commer c al-Temperature default

Industrial-Temperature option;

exceeds 85°C

Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to

"0." A13 is not used in this device.

AS4DDR232M72PBG

AustinSemiconductor, Inc. • (512) 339-1188 • www.austinsemiconductor.com

Rev. 0.0

07/06

iPEM

2.4 Gb SDRAM-DDR2

AS4DDR232M72PBG

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