IDT72V3653_16 datasheet(3/30 Pages) IDT

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IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple

bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-

nouscontrol.

CommunicationbetweeneachportmaybypasstheFIFOviatwomailbox

registers. Themailboxregisters'widthmatchestheselectedPortBbuswidth.

Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail

has been stored.

TwokindsofresetareavailableontheseFIFOs: ResetandPartialReset.

Resetinitializesthereadandwritepointerstothefirstlocationofthememoryarray

andselectsserialflagprogramming,parallelflagprogramming,oroneoffive

possibledefaultflagoffsetsettings,8,16,64,256or1,024.

PartialResetalsosetsthereadandwritepointerstothefirstlocationofthe

memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,

programmingmethodandpartialflagdefaultoffsets)areretained. PartialReset

is useful since it permits flushing of the FIFO memory without changing any

configurationsettings.

TheFIFOhasRetransmitcapability,aRetransmitisperformedafterfour

clockcyclesofCLKAandCLKB,bytakingtheRetransmitpin, RTLOWwhile

theRetransmitModepin,RTMisHIGH.WhenaRetransmitisperformedthe

readpointerisresettothefirstmemorylocation.

Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,

the first word written to an empty FIFO is deposited into the memory array. A

read operation is required to access that word (along with all other words

residing in memory). In the First Word Fall Through mode (FWFT), the first

wordwrittentoanemptyFIFOappearsautomaticallyontheoutputs,noread

operationrequired(Nevertheless,accessingsubsequentwordsdoesneces-

sitate a formal read request). The state of the BE/FWFT pin during Reset

determinesthemodeinuse.

The FIFO has a combined Empty/Output Ready Flag (EF/OR ) and a

combined Full/Input Ready Flag (FF/IR). The EF and FF functions are

selected in the IDT Standard mode. EF indicates whether or not the FIFO

memory is empty. FF shows whether the memory is full or not. The IR and

OR functions are selected in the First Word Fall Through mode. IR indicates

whetherornottheFIFOhasavailablememorylocations. ORshowswhether

the FIFO has data available for reading or not. It marks the presence of valid

dataontheoutputs.

TheFIFOhasaprogrammableAlmost-Emptyflag(AE)andaprogram-

mable Almost-Full flag (AF). AE indicates when a selected number of words

remainintheFIFOmemory. AF indicateswhentheFIFOcontainsmorethan

a selected number of words.

FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata

intoitsarray. EF/ORandAEaretwo-stagesynchronizedtotheportclockthat

reads data from its array. Programmable offsets for AE and AF are loaded

inparallelusingPortAorinserialviatheSDinput.Fivedefaultoffsetsettings

are also provided. The AE threshold can be set at 8, 16, 64, 256 or 1,024

locations from the empty boundary and the AF threshold can be set at 8, 16,

64,256or1,024locationsfromthefullboundary. Allthesechoicesaremade

using the FS0, FS1 and FS2 inputs during Reset.

InterspersedParityisavailableandcanbeselectedduringaMasterReset

oftheFIFO.IfInterspersedParityisselectedthenduringparallelprogramming

oftheflagoffsetvalues,thedevicewillignoredatalineA8.IfNon-Interspersed

Parity is selected then data line A8 will become a valid bit.

Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.

InFirstWordFallThroughmode,morethanonedevicemaybeconnectedin

seriestocreategreaterworddepths. Theadditionofexternalcomponentsis

unnecessary.

If,atanytime,theFIFOisnotactivelyperformingafunction,thechipwill

automatically power down. During the power down state, supply current

consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol

inputs)willimmediatelytakethedeviceoutofthePowerDownstate.

TheIDT72V3653/72V3663/72V3673arecharacterizedforoperationfrom

°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by

special order. They are fabricated using high speed, submicron CMOS

technology.

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