IDT72V3653_16 datasheet(13/30 Pages) IDT

13 / 30 page

COMMERCIALTEMPERATURERANGE

IDT72V3653/72V3663/72V3673 3.3V CMOS SyncFIFOTM WITH

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through at least two flip-flop

stages. Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability

of metastable events when CLKA and CLKB operate asynchronously to one

another. FF/IR, and AF are synchronized to CLKA. EF/OR and AE are

synchronizedtoCLKB. Table4 shows therelationshipofeachportflagtothe

number of words stored in memory.

EMPTY/OUTPUTREADYFLAGS(EF/OR)

These are dual purpose flags. In the FWFT mode, the Output Ready

(OR) function is selected. When the Output-Ready flag is HIGH, new data is

present in the FIFO output register. When the Output Ready flag is LOW, the

previousdatawordispresentintheFIFOoutputregisterandattemptedFIFO

reads are ignored.

IntheIDTStandardmode,theEmptyFlag(EF)functionisselected. When

the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to

the output register. When the Empty Flag is LOW, the previous data word is

present in the FIFO output register and attempted FIFO reads are ignored.

TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock

that reads data from its array (CLKB). For both the FWFT and IDT Standard

modes,theFIFOreadpointerisincrementedeachtimeanewwordisclocked

to its output register. The state machine that controls an Output Ready flag

monitors a write pointer and read pointer comparator that indicates when the

FIFOmemorystatusisempty,empty+1,orempty+2.

InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted

totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReadyflag

synchronizingclock.Therefore,anOutputReadyflagisLOWifawordinmemory

isthenextdatatobesenttotheFlFOoutputregisterandthreecyclesoftheport

ClockthatreadsdatafromtheFIFOhavenotelapsedsincethetimetheword

waswritten. TheOutputReadyflagoftheFIFOremainsLOWuntilthethirdLOW-

to-HIGHtransitionofthesynchronizingclockoccurs,simultaneouslyforcingthe

Output Ready flag HIGH and shifting the word to the FIFO output register.

In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty

Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo

cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW

if a word in memory is the next data to be sent to the FlFO output register and

twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsedsince

thetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOWuntil

thesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,forcing

the Empty Flag HIGH; only then can data be read.

ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing

clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs

attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle

can be the first synchronization cycle (see Figures 11 and 12).

FULL/INPUT READY FLAGS (FF/IR)

Thisisadualpurposeflag. InFWFTmode,theInputReady(IR)function

isselected. InIDTStandardmode,theFullFlag(FF) functionisselected. For

bothtimingmodes,whentheFull/InputReadyflagisHIGH,amemorylocation

is free in the FIFO to receive new data. No memory locations are free when

theFull/InputReadyflagisLOWandattemptedwritestotheFIFOareignored.

TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat

writesdatatoitsarray(CLKA). ForbothFWFTandIDTStandardmodes,each

timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine

that controls a Full/Input Ready flag monitors a write pointer and read pointer

comparatorthatindicateswhentheFlFO memorystatusisfull,full-1,orfull-2.

FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready

to be written to in a minimum of two cycles of the Full/Input Ready flag

synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than

twocyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsince

the next memory write location has been read. The second LOW-to-HIGH

transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets

the Full/Input Ready flag HIGH.

ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock

beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat

timetSKEW1orgreateraftertheread. Otherwise,thesubsequentclockcycle

can be the first synchronization cycle (see Figures 13 and 14).

ALMOST-EMPTYFLAG(AE)

The Almost-Empty flag of a FIFO is synchronized to the port clock that

readsdatafromitsarray(CLKB). ThestatemachinethatcontrolsanAlmost-

Emptyflagmonitorsawritepointerandreadpointercomparatorthatindicates

whentheFIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-

empty+2. TheAlmost-EmptystateisdefinedbythecontentsofregisterX. These

registersareloadedwithpresetvaluesduringaFIFOreset,programmedfrom

Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag

offset programming section). An Almost-Empty flag is LOW when its FIFO

contains X or less words and is HIGH when its FIFO contains (X+1) or more

words. NotethatadatawordpresentintheFIFOoutputregisterhasbeenread

frommemory.

TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizing

clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew

leveloffill. Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormore

wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed

sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag

issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclock

after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH

transitionofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchro-

nizationcycleifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFO

to(X+1)words. Otherwise,thesubsequentsynchronizingclockcyclemaybe

the first synchronization cycle. (See Figure 15).

ALMOST-FULL FLAG (AF)

TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites

datatoitsarray. ThestatemachinethatcontrolsanAlmost-Fullflagmonitors

a write pointer and read pointer comparator that indicates when the FIFO

memorystatusisalmost-full,almost-full-1,oralmost-full-2. TheAlmost-Fullstate

isdefinedbythecontentsofregisterY.Theseregistersareloadedwithpreset

values during a FlFO reset or, programmed from Port A, or programmed

serially (see Almost-Empty flag and Almost-Full flag offset programming

section). AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOis

greaterthanorequalto(2,048-Y),(4,096-Y),or(8,192-Y)fortheIDT72V3653,

IDT72V3663,orIDT72V3673respectively. AnAlmost-FullflagisHIGHwhen

the number of words in its FIFO is less than or equal to [2,048-(Y+1)],

[4,096-(Y+1)], or [8,192-(Y+1)] for the IDT72V3653, IDT72V3663, or

IDT72V3673 respectively. Note that a data word present in the FIFO output

TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock

are required after a FIFO read for its Almost-Full flag to reflect the new level

offill.Therefore,theAlmost-FullflagofaFIFOcontaining[2,048/4,096/8,192-

(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave

not elapsed since the read that reduced the number of words in memory to

[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second

LOW-to-HIGH transition of its synchronizing clock after the FIFO read that

reduces the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A

LOW-to-HIGHtransitionofanAlmost-Fullflagsynchronizingclockbeginsthe

IDT72V3653 Scheda tecnica(PDF) 13 Page - Integrated Device Technology

IDT72V3653 Scheda tecnica(HTML) 13 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Scheda tecnica Scarica

Link URL