11

COMMERCIALTEMPERATURERANGE

BUS-MATCHING 2,048 x 36, 4,096 x 36, and 8,192 x 36

NOTE:

1. X register holds the offset for AE; Y register holds the offset for AF.

2. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.

3. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.

4. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.

— PRESET VALUES

ToloadaFIFO’sAlmost-EmptyflagandAlmost-FullflagOffsetregisters

withoneofthefivepresetvalueslistedinTable1,theflagselectinputsmustbe

HIGHorLOWduringareset. Forexample,toloadthepresetvalueof64into

X and Y, FS0, FS1 and FS2 must be HIGH when RS1 returns HIGH. For

the relevant preset value loading timing diagram, see Figure 3.

— PARALLEL LOAD FROM PORT A

ToprogramtheXandYregistersfromPortA,performaResetwithFS2

HIGH or LOW and FS0 and FS1 LOW during the LOW-to-HIGH transition of

RS1. ThestateofFS2atthispointofresetwilldeterminewhethertheparallel

programming method has Interspersed Parity or Non-Interspersed Parity.

RefertoTable1forFlagProgrammingFlagOffsetsetup.Itisimportanttonote

thatonceparallelprogramminghasbeenselectedduringaMasterResetby

holding both FS0 & FS1 LOW, these inputs must remain LOW during all

subsequent FIFO operation. They can only be toggled HIGH when future

MasterResetsareperformedandotherprogrammingmethodsaredesired.

Afterthisresetiscomplete,thefirsttwowritestotheFIFOdonotstoredata

inRAM. ThefirsttwowritecyclesloadtheoffsetregistersintheorderY,X. On

thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure

5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag

Offset Values after Reset (IDT Standard and FWFT modes), for a detailed

timingdiagram.ForNon-InterspersedParitymodethePortAdatainputsused

bytheOffsetregistersare(A10-A0),(A11-A0),or(A12-A0)fortheIDT72V3653,

IDT72V3663,orIDT72V3673,respectively.ForInterspersedParitymodethe

PortAdatainputsusedbytheOffsetregistersare(A11-A9,A7-A0),(A12-A9,

A7-A0),or(A13-A9,A7-A0)fortheIDT72V3653,IDT72V3663,orIDT72V3673,

respectively. Thehighestnumberedinputisusedasthemostsignificantbitof

the binary number in each case. Valid programming values for the registers

rangefrom1to2,044fortheIDT72V3653;1to4,092fortheIDT72V3663;and

1to8,188fortheIDT72V3673. Afteralltheoffsetregistersareprogrammed

from Port A, the FIFO begins normal operation.

INTERSPERSED PARITY

Interspersed Parity is selected during a Master Reset of the FIFO. Refer

toTable1fortheset-upconfigurationofInterspersedParity.TheInterspersed

Parityfunctionallowstheusertoselectthelocationoftheparitybitsintheword

loaded into the parallel port (A0-An) during programming of the flag offset

values.IfInterspersedParityisselectedthenduringparallelprogrammingof

the flag offset values, the device will ignore data line A8. If Non-Interspersed

ParityisselectedthendatalineA8willbecomeavalidbit.IfInterspersedParity

isselectedserialprogrammingoftheoffsetvaluesisnotpermitted,onlyparallel

programming can be done.

— SERIAL LOAD

ToprogramtheXandYregistersserially,initiateaResetwithFS2LOW,

FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-HIGHtransitionofRS1.

After this reset is complete, the X and Y register values are loaded bit-wise

through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the

FS1/SENinputisLOW.Thereare22-,24-or26-bitwritesneededtocomplete

the programming for the IDT72V3653, IDT72V3663 or the IDT72V3673,

respectively. ThetworegistersarewrittenintheorderY,X. Eachregistervalue

canbeprogrammedfrom1to2,044(IDT72V3653),1to4,092(IDT72V3663)

or 1 to 8,188 (IDT72V3673).

Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/

Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/

IRissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbitisloaded

to allow normal FIFO operation.

See Figure 6, Serial Programming of the Almost-Full Flag and Almost-

Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).

FIFO WRITE/READ OPERATION

ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect

(CSA)andPortAWrite/Readselect(W/RA). TheA0-A35linesareintheHigh-

impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are

active outputs when both CSA and W/RA are LOW.

DataisloadedintotheFIFOfromtheA0-A35inputsonaLOW-to-HIGH

transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is

LOW,andFF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent

of any concurrent reads on Port B.

ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception

thatthePortBWrite/Readselect(W/RB)istheinverseofthePortAWrite/Read

select(W/RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe

PortBChipSelect(CSB)andPortBWrite/Readselect(W/RB). TheB0-B35

linesareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBisLOW.

The B0-B35 lines are active outputs when CSB is LOW and W/RB is HIGH.

FS2

FS1/SEN

FS0/SD

RS1

HHH

↑

64

HH

L

↑

16

HL

H

↑

8

LH

H

↑

256

LL

H

↑

1,024

LH

L

↑

Serial programming via SD

HL

L

↑

LLL

↑

TABLE 1 — FLAG PROGRAMMING