70T653MS12BCGI datasheet(17/24 Pages) IDT

17 / 24 page

IDT70T653M

High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table III — Interrupt Flag(1,4)

Waveform of Interrupt Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.

4. Timing depends on which enable signal (CE or R/W) is asserted last.

5. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTES:

1. Assumes BUSYL = BUSYR =VIH. CE0X = VIL and CE1X = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTL and INTR must be initialized at power-up.

5679 drw 18

ADDR"A"

INTERRUPT SET ADDRESS

CE"A"(3)

W"A"

tAS

tWC

tWR

(4)

(5)

tINS

(4)

INT"B"

(2)

5679 drw 19

ADDR"B"

INTERRUPT CLEAR ADDRESS

CE"B"(3)

OE"B"

tAS

tRC

(4)

tINR

(4)

INT"B"

(2)

Left Port

Right Port

Function

R/WL

CEL

OEL

A18L-A0L

INTL

R/WR

CER

OER

A18R-A0R

INTR

7FFFF

L(2)

Set Right INTR Flag

7FFFF

H(3)

Reset Right INTR Flag

L(3)

7FFFE

Set Left INTL Flag

7FFFE

H(2)

Reset Left INTL Flag

5679 tbl 17

70T653MS12BCGI Scheda tecnica(PDF) 17 Page - Integrated Device Technology

70T653MS12BCGI Scheda tecnica(HTML) 17 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Scheda tecnica Scarica

Link URL