PPC34C60 datasheet(16/58 Pages) SMSC

16 / 58 page

SMSC DS – PPC34C60

Page 16

Rev. 06/01/2001

ADVANCED INFORMATION

3.3 Device Addressing

The Bi-Directional Parallel Peripheral Interface protocol, defined by the IEEE STD 1284 (Reference 1), describes two basic

types of 8-bit information transfers: data read/write operations and address read/write operations. The PPC34C60's bus

and internal registers are accessed via data read/write operations.

The PPC34C60's address mode is set through an SPP, EPP, or ECP address write operation. Table 1 specifies the control

signals used by each protocol to perform Address and Data Cycles and to indicate reverse data flow. Refer to the IEEE

STD 1284 (Reference 1) for further information.

Table 1 - Key Address/Data Cycle Signals

SIGNAL

SPP

EPP

ECP

Address

Strobe

SEL

STB(ALF=0)

Data

Strobe

STB

ALF

STB(ALF=1)

Reverse Channel

Signal

INIT=0

IMPLICIT

INIT = 0

The Parallel Port provides a byte-wide parallel data path. FIGURE 4 defines the data bits of this parallel port data path

during an address write operation to the PPC34C60.

FIGURE 4 - PARALLEL PORT ADDRESS WRITE AND DATA BITS

Bus or Register Address

Type of Access

Write/Read

Required for ECP

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