PPC34C60 datasheet(53/58 Pages) SMSC

53 / 58 page

SMSC DS – PPC34C60

Page 53

Rev. 06/01/2001

ADVANCED INFORMATION

FIGURE 23 - DRAM READ CYCLE TIMING

When the DRAM bus width (4, 8 or 16 bits) is narrower than the Host bus (always 8-bits) or the Peripheral bus (8 or 16 bits)

than the PPC34C60 will implement fast page mode DRAM cycles to complete the data transfer. These page mode

transfers are performed for DMA as well as Host DRAM access.

See DRAM Read Cycle Timing Parameters.

DRAM READ CYCLE TIMING

PARAMETER

MIN

TYP

MAX

UNITS

10-bit DRAM row address valid to nRD asserted.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

10-bit DRAM row address valid to nRAS asserted.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

nRAS asserted to valid 10-bit DRAM column

address.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

10-bit DRAM column address valid to nCAS

asserted.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

10-bit DRAM column address incremented and at the

same time the data is latched into the PPC34C60

following nCAS asserted.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

nCAS deasserted after the column address has been

updated and the data has been latched by the

PPC34C60.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

nCAS deasserted pulse width during page mode

accesses.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

nCAS asserted to valid data, i.e., maximum

acceptable DRAM access time.

[1BCLK

-10]

nCAS deasserted to DRAM releasing data from the

bus.

[1BCLK

-10]

t10

nCAS and nRAS both deasserted to nRD

deasserted.

[1 SCLK]

t10

Data Valid

Row Addr

Col Addr

Col Addr +2

Col Addr +1

SAB

Data Valid

Col Addr bits 8 & 9

SAB

MA[8:9]

SA[0:7]

nCAS

nRAS

nRD

nWR

SD[0:15]

BUSCLK

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