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STGAP1STR Scheda tecnica(PDF) 56 Page - STMicroelectronics |
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STGAP1STR Scheda tecnica(HTML) 56 Page - STMicroelectronics |
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56 / 67 page ![]() Programming manual STGAP1S 56/67 DocID027190 Rev 3 The VLONth bits set the UVLO threshold on the negative power supply according to Table 40. Setting the parameter to zero disables the UVLO protection of the VL supply. The VHONth bits set the UVLO threshold on the positive power supply according to Table 41. Setting the parameter to zero disables the UVLO protection of the VH supply. 9.2.5 CFG5 register (isolated side) The CFG4 register has the structure of Table 42. Table 39. UVLO protection management UVLOlatch UVLO protection management 0 UVLO protection is not latched 1 UVLO protection is latched Table 40. VL negative supply voltage UVLO threshold VLONth [1 ... 0] Negative supply voltage UVLO threshold [V] 0 0 Disabled 01 -3 10 -5 11 -7 Table 41. VH positive supply voltage UVLO threshold VHONth [1 ... 0] Positive supply voltage UVLO threshold [V] 0 0 Disabled 01 10 10 12 11 14 Table 42. CFG5 register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2LTO_EN CLAMP_EN DESAT_EN SENSE_EN Default/reset 0 1 1 0 |
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