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STGAP1STR Scheda tecnica(PDF) 20 Page - STMicroelectronics |
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STGAP1STR Scheda tecnica(HTML) 20 Page - STMicroelectronics |
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20 / 67 page ![]() Electrical characteristics STGAP1S 20/67 DocID027190 Rev 3 SPI(1) tCKmax 5 Maximum SPI clock frequency 5MHz trCK tfCK SPI clock rise and fall time CL = 30 pF 25 ns thCK tlCK SPI clock high and low time 75 ns tsetCS 4 CS setup time 350 ns tholCS CS hold time 10 ns tdesCS CS deselect time(3) Local register read 800 ns Remote register read 30 µs Start configuration 22 Stop configuration 5 Reset status register 50 Reset remote register 25 Any other command 700 ns tsetSDI 3 SDI setup time 25 ns tholSDI SDI hold time 20 ns tenSDO 2 SDO enable time 38 ns tdisSDO SDO disable time 47 ns tvSDO SDO valid time 57 ns tholSDO SDO hold time 37 ns tSDLCSL 4,11 SD falling to CS falling 350 ns tCSHSDH 4,11 CS rising to SD rising 350 ns 1. Characterization data, not tested in production. 2. The actual waiting time depends on the gate charge size. 3. See Table 22 on page 50 and Section 9.1.3 on page 48. Table 6. DC operation electrical characteristics (Tj = -40 to 125 °C, VDD = 5 V; VH = 15 V, VL = GNDISO) (continued) Symbol Pin Parameter Test condition Min. Typ. Max. Unit |
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