AD9957SLASHPCBZ datasheet(29/62 Pages) AD

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AD9957

Data Sheet

Rev. E | Page 28 of 61

LOAD/RETRIEVE RAM OPERATION

Loading or retrieving the RAM contents is a three-step process.

Program the RAM segment registers with start and end

addresses defining the boundaries of each independent

RAM segment.

Toggle the RT pin with the appropriate transition to select

the desired RAM segment register.

Using the serial I/O port, write (or read) the address range

specified by the selected RAM segment register.

Figure 40 shows the RAM block diagram when used for loading

or retrieve operations.

RAM

STATE

MACHINE

END ADDRESS

START ADDRESS

ADDRESS STEP RATE

RAM MODE

CLK

BASEBAND DATA CLOCK

DDS CLOCK

UP/DOWN COUNTER

I CHANNEL

Q CHANNEL

U/D

(MSBs)

(LSBs)

NOTES

1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.

RAM

SEGMENT

REGISTERS

SCLK

SDIO

SDO

I/O_RESET

Figure 40. RAM Load/Retrieve Operation

During a load or retrieve operation, the state machine controls

an up/down counter to step through the required RAM locations.

The counter is synchronized with the serial I/O port so that the

serial/parallel conversion of the 32-bit words is correctly timed

with the generation of the appropriate RAM address to properly

execute the desired read or write operation. The up/down

counter always increments through the address range during

serial I/O port operations.

Because the RAM segment registers are completely independent,

it is possible to define overlapping address ranges. However,

doing so causes the overlapping address locations to be over-

written by the most recent write operation. It is recommended

that the user avoid defining overlapping address ranges.

RAM PLAYBACK OPERATION

When the RAM has been loaded, it can be used for playback

operation. The destination of the playback data is selected via

the RAM playback destination bit. The active RAM segment

The active RAM segment register directs the internal state

machine by defining the RAM address range occupied by the

data and the RAM playback mode. It also defines the playback

rate when the playback destination is the baseband scaling

multipliers.

Although RAM load/retrieve operations via the serial I/O port

take precedence over playback, it is recommended that the user

not attempt RAM access via the serial I/O port when the RAM

enable bit is set.

Figure 41 is a block diagram showing the functional compo-

nents used for RAM playback operation when the internal

destination is the baseband scaling multipliers.

RAM

STATE

MACHINE

END ADDRESS

START ADDRESS

ADDRESS STEP RATE

RAM MODE

CLK

BASEBAND DATA CLOCK

DDS CLOCK

UP/DOWN COUNTER

I CHANNEL

Q CHANNEL

RAM

SEGMENT

REGISTERS

U/D

(MSBs)

(LSBs)

NOTES

1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.

SCLK

SDIO

SDO

I/O_RESET

Figure 41. RAM Playback to Baseband Scaling Multipliers

During playback to the baseband scaling multipliers, the

address step rate word in the active RAM segment register sets

the rate at which RAM data samples are delivered to the

multipliers. The following equations define the RAM sample

rate and sample interval (Δt):

Rate

Sample

RAM

SYSCLK



SYSCLK





where:

R is the rate interpolation factor for the CCI filter.

M is the 16-bit value of the address step rate word stored in the

active RAM segment register.

If the RAM enable bit is set and the baseband scaling multi-

pliers are selected as the playback destination, then assertion

of an I/O update or profile change causes the multipliers to be

driven with a static value of zero. A subsequent state change on

the RT pin causes the multipliers to be driven by the data played

back from the RAM instead of the static zero value.

Figure 42 is a block diagram showing RAM playback operation

when the internal destination is the baseband data path. During

playback to the baseband data path, the state machine increments/

decrements the RAM address at the baseband data rate (the

address step rate must be set to 1).

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