AD9957SLASHPCBZ datasheet(37/62 Pages) AD

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AD9957

Data Sheet

Rev. E | Page 36 of 61

PLL CHARGE PUMP

The charge pump current (ICP) is programmable to provide the

user with additional flexibility to optimize the PLL performance.

Table 8 lists the bit settings vs. the nominal charge pump current.

Table 8. PLL Charge Pump Current

ICP (CFR3<21:19>)

Charge Pump Current, ICP (μA)

000

212

001

237

010

262

011

287

100

312

101

337

110

363

111

387

EXTERNAL PLL LOOP FILTER COMPONENTS

The PLL_LOOP_FILTER pin provides a connection interface to

attach the external loop filter components. The ability to use

custom loop filter components gives the user more flexibility to

optimize the PLL performance. The PLL and external loop filter

components are shown in Figure 52.

PFD

PLL_LOOP_FILTER

VCO

÷N

PLL OUT

PLL IN

AVDD

REFCLK PLL

Figure 52. REFCLK PLL External Loop Filter

In the prevailing literature, this configuration yields a third-

order, Type II PLL. To calculate the loop filter component

values, begin with the feedback divider value (N), the gain of

the phase detector (KD), and the gain of the VCO (KV) based on

the programmed VCO SEL bit settings (see Table 1 for KV). The

loop filter component values depend on the desired open-loop

bandwidth (fOL) and phase margin (φ), as follows:



















sin

(7)

 

2

tan







(8)

 

 











 



cos

sin

)

(

(9)

where:

KD equals the programmed value of ICP.

KV is taken from Table 1.

Ensure that proper units are used for the variables in Equation 7

through Equation 9. ICP must be in amps, not μA as appears in

Table 8; KV must be in Hz/V, not MHz/V as listed in Table 1; the

loop bandwidth (fOL) must be in Hz; the phase margin (φ) must

be in radians. Furthermore, to limit the phase noise contribution of

the internal VCO, the loop bandwidth must be 1 MHz or greater.

For example, suppose the PLL is programmed such that

ICP = 287 μA, KV = 850 MHz/V, and N = 25. If the desired loop

bandwidth and phase margin are 1 MHz and 45°, respectively,

the loop filter component values are R1 = 777.3 Ω, C1 = 494.3 pF,

and C2 = 102.4 pF.

PLL LOCK INDICATION

When the PLL is in use, the PLL_LOCK pin provides an active

high indication that the PLL has locked to the REFCLK input

signal. When the PLL is bypassed, the PLL_LOCK pin defaults

to Logic 0.

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