| Motore di ricerca datesheet componenti elettronici |
|
ST25DV64K Scheda tecnica(PDF) 87 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST25DV64K Scheda tecnica(HTML) 87 Page - STMicroelectronics |
|
87 / 220 page ![]() DocID027603 Rev 4 87/220 ST25DV04K ST25DV16K ST25DV64K I2C operation 219 6.1.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal write cycle. 6.1.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether a bus master or a slave device, releases the serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA low to acknowledge the receipt of the eight data bits. 6.1.4 Data input During data input, the device samples serial data (SDA) on the rising edge of the serial clock (SCL). For correct device operation, the SDA must be stable during the rising edge of the SCL, and the SDA signal must change only when the SCL is driven low. 6.2 I2C timeout During the execution of an I²C operation, RF communications are not possible. To prevent RF communication freezing due to inadvertent unterminated instructions sent to the I²C bus, the ST25DVxxx features a timeout mechanism that automatically resets the I²C logic block. 6.2.1 I2C timeout on Start condition I2C communication with the ST25DVxxx starts with a valid Start condition, followed by a device select code. If the delay between the Start condition and the following rising edge of the Serial Clock (SCL) that samples the most significant of the Device Select exceeds the tSTART_OUT time (see Table 209: I2C AC characteristics up to 85°C and Table 210: I2C AC characteristics up to 125°C), the I²C logic block is reset and further incoming data transfer is ignored until the next valid Start condition. |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |