ST25DV64K datasheet(89/220 Pages) STMICROELECTRONICS

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ST25DV04K ST25DV16K ST25DV64K

I2C operation

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6.4

I2C Write operations

Following a Start condition, the bus master sends a device select code with the Read/Write

bit (RW) reset to 0. The device acknowledges this, and waits for two address bytes. The

device responds to each address byte with an acknowledge bit, and then waits for the data

byte.

Each data byte in the memory has a 16-bit (two-byte wide) address. The most significant

byte (see Table 53: Address most significant byte) is sent first, followed by the least

significant byte (see Table 54: Address least significant byte). Bits b15 to b0 form the

address of the byte in memory.

When the bus master generates a Stop condition immediately after the Ack bit (in the tenth-

bit time slot), either at the end of a byte write or a sequential write, the internal write cycle is

triggered. A Stop condition at any other time slot does not trigger the internal write cycle.

After the Stop condition, the delay tW, and the successful completion of a Write operation,

the device’s internal address counter is incremented automatically, to point to the next byte

address after the last one that was modified.

After an unsuccessful write operation, ST25DVxxx enters in I2C dead state: internal

address counter is not incremented, and ST25DVxxx is waiting for a full new I2C instruction.

During the internal write cycle, the serial data (SDA) signal is disabled internally, and the

device does not respond to any requests.

Caution:

I2C Writing data in user or system memory (EEPROM), transit via the 256-Bytes fast

transfer mode's buffer. Consequently fast transfer mode must be deactivated before starting

any write operation in user or system memory, otherwise command will be NotACK,

programming is not done and device goes in standby mode.

Table 52. Operating modes

Mode

RW bit

Bytes

Initial sequence

Current address read

Start, device select, RW = 1

Random address read

Start, device select, RW = 0, address

reStart, device select, RW = 1

Sequential read

≥ 1

Similar to current or random address read

Byte write

Start, device select, RW = 0

Sequential write

≤ 256 byte

Start, device select, RW = 0

Table 53. Address most significant byte

b15

b14

b13

b12

b11

b10

Table 54. Address least significant byte

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