ST25DV64K datasheet(88/220 Pages) STMICROELECTRONICS

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I2C operation

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Figure 25. I²C timeout on Start condition

6.2.2

I2C timeout on clock period

During data transfer on the I²C bus, if the serial clock pulse width high (tCHCL) or serial clock

pulse width low (tCLCH) exceeds the maximum value specified in Table 209: I2C AC

characteristics up to 85°C and Table 210: I2C AC characteristics up to 125°C, the I²C logic

block is reset and any further incoming data transfer is ignored until the next valid Start

condition.

6.3

Device addressing

To start a communication between the bus master and the slave device, the bus master

must initiate a Start condition. Following this, the bus master sends the device select code,

shown in Table 51: Device select code (on Serial Data (SDA), the most significant bit first).

The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable

“Address” (E2,1,1). To address the memory array, the 4-bit device type identifier is 1010b.

Refer to Table 51: Device select code.

The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

Table 51. Device select code

Device type identifier(1)

1. The most significant bit, b7, is sent first.

Chip Enable address

Device select code

1010

E2(2)

2. E2 is not connected to any external pin. It is however used to address the ST25DVxxx as

described in Section 4: Memory management

E2 = 0, access to user memory, Dynamic registers or Mailbox.

E2 =1, access to system area.

ST25DV64K Scheda tecnica(PDF) 88 Page - STMicroelectronics