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SAFC161RI Scheda tecnica(PDF) 44 Page - Siemens Semiconductor Group |
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SAFC161RI Scheda tecnica(HTML) 44 Page - Siemens Semiconductor Group |
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44 / 60 page ![]() Semiconductor Group 44 1998-05-01 C161RI Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. AC Characteristics Multiplexed Bus V DD = 4.5 - 5.5 V; V SS = 0 V T A = 0 to + 70 °C for SAB-C161RI T A = – 40 to + 85 °C for SAF-C161RI C L = 100 pF ALE cycle time = 6 TCL + 2 t A + tC + tF (186 ns at 16 MHz CPU clock without waitstates) Description Symbol Values ALE Extension t A TCL × <ALECTL> Memory Cycle Time Waitstates t C 2TCL × (15 - <MCTC>) Memory Tristate Time t F 2TCL × (1 - <MTTC>) Parameter Symbol Max. CPU Clock = 16 MHz Variable CPU Clock 1/2TCL = 1 to 16 MHz Unit min. max. min. max. ALE high time t 5 CC 21 + t A – TCL - 10 + t A –ns Address setup to ALE t 6 CC 15 + t A – TCL - 16 + t A –ns Address hold after ALE t 7 CC 21 + t A – TCL - 10 + t A –ns ALE falling edge to RD, WR (with RW-delay) t 8 CC 21 + t A – TCL - 10 + t A –ns ALE falling edge to RD, WR (no RW-delay) t 9 CC – 10 + t A – – 10 + t A –ns Address float after RD, WR (with RW-delay) t 10 CC –6– 6 ns Address float after RD, WR (no RW-delay) t 11 CC –37 – TCL + 6 ns RD, WR low time (with RW-delay) t 12 CC 53 + t C – 2TCL - 10 + t C –ns RD, WR low time (no RW-delay) t 13 CC 84 + t C – 3TCL - 10 + t C –ns |
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