AD9144BCPZ datasheet(44/125 Pages) AD

44 / 125 page

AD9144

Data Sheet

Rev. B | Page 44 of 125

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system.



SYSREF± signal distribution skew within the system must

be less than the desired uncertainty.



SYSREF± setup and hold time requirements must be met

for each device in the system.



The total latency variation across all lanes, links, and

devices must be ≤10 PClock periods. This includes both

variable delays and the variation in fixed delays from lane

to lane, link to link, and device to device in the system.

Link Delay

The link delay of a JESD204B system is the sum of fixed and

variable delays from the transmitter, channel, and receiver as

shown in Figure 48.

For proper functioning, all lanes on a link must be read during

the same LMFC period. Section 6.1 of the JESD204B

specification states that the LMFC period must be larger than

the maximum link delay. For the AD9144, this is not necessarily

the case; instead, the AD9144 uses a local LMFC for each link

(LMFCRx) that can be delayed from the SYSREF aligned LMFC.

Because the LMFC is periodic, this can account for any amount

of fixed delay. As a result, the LMFC period must only be larger

than the variation in the link delays, and the AD9144 can achieve

proper performance with a smaller total latency. Figure 46 and

Figure 47 show a case where the link delay is larger than an

LMFC period. Note that it can be accommodated by delaying

LMFCRx.

ILAS

DATA

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

EARLY ARRIVING

LMFC REFERENCE

LATE ARRIVING

LMFC REFERENCE

Figure 46. Link Delay > LMFC Period Example

ILAS

DATA

FRAME CLOCK

POWER CYCLE

VARIANCE

LMFC

ALIGNED DATA

LMFCRX

LMFC_DELAY

LMFC REFERENCE FOR ALL POWER CYCLES

Figure 47. LMFC_DELAY to Compensate for Link Delay > LMFC

ILAS

FIXED DELAY

VARIABLE

DELAY

POWER CYCLE

VARIANCE

DATA

LMFC

ALIGNED DATA

AT Rx OUTPUT

DATA AT

Tx INPUT

DATA

DSP

CHANNEL

LOGIC DEVICE

(JESD204B Tx)

JESD204B Rx

DAC

LINK DELAY = DELAYFIXED + DELAYVARIABLE

Figure 48. JESD204B Link Delay = Fixed Delay + Variable Delay

AD9144BCPZ Scheda tecnica(PDF) 44 Page - Analog Devices

AD9144BCPZ Scheda tecnica(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL