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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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AD9144BCPZ Scheda tecnica(PDF) 58 Page - Analog Devices |
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AD9144BCPZ Scheda tecnica(HTML) 58 Page - Analog Devices |
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58 / 125 page  AD9144 Data Sheet Rev. B | Page 58 of 125 Table 57. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 9 Address Setting Description 0x453 0x01 or 0x81 Register 0x453[7] = 0 or 1: scrambling disabled or enabled, Register 0x453[4:0] = 0x1: L = 2 lanes per link 0x454 0x00 Register 0x454[7:0] = 0x00: F = 1 octet per frame 0x455 0x1F Register 0x455[4:0] = 0x1F: K = 32 frames per multiframe 0x456 0x00 Register 0x456[7:0] = 0x00: M = 1 converter per link 0x457 0x0F Register 0x457[7:6] = 0x0: always set CS = 0; Register 0x457[4:0] = 0x0F: N = 16, always set to 16-bit resolution 0x458 0x0F or 0x2F Register 0x458[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458[4:0] = 0xF: NP = 16 bits per sample 0x459 0x20 Register 0x459[7:5] = 0x1: Set to JESD204B version; Register 0x459[4:0] = 0x0: S = 1 (sample/converter)/frame 0x45A 0x01 Register 0x45A[7] = 1: HD = 1; Register 0x45A[4:0] = 0x00: always set CF = 0 0x46C 0x03 Register0x46C[7:0] = 0x03: deskew Link Lane 0 and Link Lane 1 0x476 0x01 Register 0x476[7:0] = 0x01: F = 1 octet per frame 0x47D 0x03 Register 0x47D[7:0] = 0x03: enable Link Lane 0 and Link Lane 1 1 OCTET PER LANE 16-BIT NIBBLE GROUP 1 SAMPLE PER DAC0 SERIAL JESD204B DATA (L = 2) SAMPLES SPLIT ACROSS LANES (HD = 1) NIBBLE GROUP 0 CONVERTER 0, SAMPLE 0 D15 ... D0 LANE 0, OCTET 0 LANE 1, OCTET 0 1 CONVERTER (F = 1) (N = 16) CONVERTER PER FRAME (S = 1) (M = 1) Figure 61. JESD204B Mode 9 Data Deframing |
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