AD9144BCPZ datasheet(13/125 Pages) AD

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Data Sheet

AD9144

Rev. B | Page 13 of 125

Pin No.

Mnemonic

Description

SVDD12

1.2 V JESD204B Receiver Supply.

VTT

1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.

SVDD12

1.2 V JESD204B Receiver Supply.

SYNCOUT0+

Positive LVDS Sync (Active Low) Output Signal Channel Link 0.

SYNCOUT0−

Negative LVDS Sync (Active Low) Output Signal Channel Link 0.

VTT

1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.

SERDIN2+

Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN2−

Serial Channel Input 2, Negative. CML compliant. SERDIN2− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SVDD12

1.2 V JESD204B Receiver Supply.

SERDIN3+

Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN3−

Serial Channel Input 3, Negative. CML compliant. SERDIN3− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SVDD12

1.2 V JESD204B Receiver Supply.

SVDD12

1.2 V JESD204B Receiver Supply.

SVDD12

1.2 V JESD204B Receiver Supply.

LDO_BYP1

LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground.

SIOVDD33

3.3 V Supply for SERDES.

SVDD12

1.2 V JESD204B Receiver Supply.

SERDIN4−

Serial Channel Input 4, Negative. CML compliant. SERDIN4− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN4+

Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SVDD12

1.2 V JESD204B Receiver Supply.

SERDIN5−

Serial Channel Input 5, Negative. CML compliant. SERDIN5− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN5+

Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

VTT

1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.

SYNCOUT1−

Negative LVDS Sync (Active Low) Output Signal Channel Link 1.

SYNCOUT1+

Positive LVDS Sync (Active Low) Output Signal Channel Link 1.

SVDD12

1.2 V JESD204B Receiver Supply.

VTT

1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.

SVDD12

1.2 V JESD204B Receiver Supply.

SERDIN6−

Serial Channel Input 6, Negative. CML compliant. SERDIN6− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN6+

Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SVDD12

1.2 V JESD204B Receiver Supply.

SERDIN7−

Serial Channel Input 7, Negative. CML compliant. SERDIN7− is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

SERDIN7+

Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage

using a calibrated 50 Ω resistor. This pin is ac-coupled only.

DVDD12

1.2 V Digital Supply.

GND

Ground. Connect GND to the ground plane.

GND

Ground. Connect GND to the ground plane.

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

PVDD12

1.2 V Supply. PVDD12 provides a clean supply.

PROTECT_OUT1

Power Detection Protection Pin Output for DAC2 and DAC3. Pin 58 is high when power protection is in process.

PROTECT_OUT0

Power Detection Protection Pin Output for DAC0 and DAC1. Pin 59 is high when power protection is in process.

IRQ

Interrupt Request (Active Low, Open Drain).

RESET

Reset. This pin is active low. CMOS levels are determined with respect to IOVDD.

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