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SSM3515CCBZ-R7 Scheda tecnica(PDF) 5 Page - Analog Devices

Il numero della parte SSM3515CCBZ-R7
Spiegazioni elettronici  Audio Amplifier
PDF  41 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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SSM3515CCBZ-R7 Scheda tecnica(HTML) 5 Page - Analog Devices

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Data Sheet
SSM3515
Rev. A| Page 5 of 41
Software master power-down indicates that the clocks are turned off. Auto power-down indicates that there is no dither or zero input
signal with clocks on; the device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular dither with
zero input signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted.
Table 2. Power Supply Current Consumption1
Edge Rate
Control
Mode
REG_EN Pin
Test Conditions
No Load
4 Ω + 15 µH
8 Ω + 33 µH
Unit
IPVDD
IREG18
IPVDD
IREG18
IPVDD
IREG18
PVDD
5 V
12 V
17 V
1.8 V
5 V
12 V
17 V
1.8 V
5 V
12 V
17 V
1.8 V
Normal
Low
Software master
power-down
0.01
0.03
0.03
7
0.01
0.03
0.03
7
0.01
0.03
0.03
7
μA
Auto power-down
0.01
0.03
0.03
54
0.01
0.03
0.03
54
0.01
0.03
0.03
54
μA
Quiescent
4.10
5.00
5.60
0.48
4.10
5.12
5.90
0.48
4.10
5.10
5.80
0.48
mA
PVDD
Software master
power-down
0.01
0.03
0.03
N/A
0.01
0.03
0.03
N/A
0.01
0.03
0.03
N/A
μA
Auto power-down
310
310
316
N/A
310
310
316
N/A
310
310
316
N/A
μA
Quiescent
4.64
5.60
6.26
N/A
4.74
5.85
6.55
N/A
4.74
5.85
6.55
N/A
mA
Low EMI
Low
Software master
power-down
0.01
0.03
0.03
7
0.01
0.03
0.03
7
0.01
0.03
0.03
7
μA
Auto power-down
0.01
0.03
0.03
54
0.01
0.03
0.03
54
0.01
0.03
0.03
54
μA
Quiescent
4.00
4.95
5.54
0.48
4.70
3.99
5.59
0.48
4.02
4.98
5.63
0.48
mA
PVDD
Software master
power-down
0.01
0.03
0.03
N/A
0.01
0.03
0.03
N/A
0.01
0.03
0.03
N/A
μA
Auto power-down
310
310
316
N/A
310
310
316
N/A
310
310
316
N/A
μA
Quiescent
4.60
5.60
6.17
N/A
4.60
5.65
6.35
N/A
4.60
5.60
6.40
N/A
mA
1 N/A means not applicable.
Table 3. Power-Down Current
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
POWER-DOWN CURRENT
VREG18/DVDD = 1.8 Vexternal, software master power-down,no BCLK/FSYNC
IPVDD
PVDD = 5 V
27
38
95
nA
PVDD = 12 V
30
39
100
nA
PVDD = 17 V
30
39
152
nA
IDVDD
VREG18/DVDD = 1.8 V external
7
27
μA
Table 4. Digital Input/Output
Parameter
Min
Typ
Max
Unit
Test Comments/Comments
INPUT VOLTAGE1
High (VIH)
BCLK, FSYNC, SCL, SDA
1.13
5.5
V
SDATA, ADDR
0.7 × VREG18/DVDD
1.98
V
Low (VIL)
BCLK, FSYNC, SDATA, SCL, SDA
−0.3
+0.54
V
ADDR
−0.3
+1.98
V
INPUT LEAKAGE
High (IIH)
1
µA
Low (IIL)
1
µA
INPUT CAPACITANCE
5
pF
OUTPUT VOLTAGE (SDATA)
High (VOH)
1.17
V
Low (VOL)
0.45
V
OUTPUT DRIVE STRENGTH1
SDA
3
5
mA
SDATA
2
24
mA
BCLK Frequency (BCLK)
2.048
24.576
MHz
Sample Rate (FSYNC)
8
192
kHz
1 The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.



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