PIFE32251B-R47MS datasheet(43/96 Pages) TI1

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TPS65094

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SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

As VSYS crosses above VSYS_UVLO_5V + VSYS_UVLO+5V_HYS, the cold-boot sequence is initiated by pulling the

PMICEN pin high followed by driving the remaining control pins high in order. SLP_S3B and SLP_S4B

may go high at the same time. SLP_S0B is not defined until the first transition to S0 after RSMRSTB

deassertion. SLP_S0B is defined for all Sx power-state transitions after the first transition to S0.

Table 6-10 lists definitions of the timing delays. These timing delays also apply to the subsequent

sequences. T0 to T10 are factory programmable to 0 ms, 2 ms, 4 ms, 8 ms, 16 ms, 24 ms, 32 ms, or

64 ms.

Table 6-10. Definition of Delays During Cold Boot Sequence

DELAY

DESCRIPTION

TYP VALUE

UNIT

PMICEN to BUCK1 (VNN) enable

PMICEN to BUCK4 (V1P8A) enable

BUCK4 PG to BUCK5 (V1P24A) enable

BUCK5 PG to RSMRSTB deassertion

SLP_S4B deassertion to SWB1_2 (V1P8U) enable

SLP_S4B deassertion to BUCK6 (VDDQ) enable

Logical AND of BUCK6 PG, SLP_S0B, SLP_S3B, and SLP_S4B to VTT enable

SLP_S0B deassertion to BUCK3 (VCCRAM) enable

Logical AND of all PGs (except BUCK2) to PCH_PWROK assertion. User selectable

from POK_DELAY register.

100

PIFE32251B-R47MS Scheda tecnica(PDF) 43 Page - Texas Instruments