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PIFE32251B-R47MS Scheda tecnica(PDF) 47 Page - Texas Instruments

Il numero della parte PIFE32251B-R47MS
Spiegazioni elettronici  PMIC for Intel Apollo Lake Platform
PDF  96 Pages
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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PIFE32251B-R47MS Scheda tecnica(HTML) 47 Page - Texas Instruments

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S0
SLP_S0B
VTT
BUCK1 (VNN)
S0
BUCK2 (VCCGI)
SLP_S3B
PCH_PWROK
S3
SWB1_2
(2)
T8
S3
S5/S4
SLP_S4B
BUCK6 (VDDQ)
T5
1.8 V
1.05 V
VID
˜ 100 µs
0 V
˜ 5 ms
0 V
SET VID by Host
BUCK3 (VCCRAM)
0 V
SWB1_2 (V1P8U)
(1)
˜ 2 ms
30 ms to 60 ms
(1) LPDDR3 and LPDDR4
(2) DDR3L
47
TPS65094
www.ti.com
SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019
Submit Documentation Feedback
Product Folder Links: TPS65094
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
6.3.5.5
S0 to S4/5 Entry and Exit
Assertion of the SLP_S4B (H
→ L) after the S3 entry pushes the sequence further down to S4/5 where
SWB1_2 (for LPDDR3 or LPDDR4) and BUCK6 are disabled. Any rails not shown are essentially the
same as the S0 to S3 entry and exit case described in Figure 6-11.
Figure 6-11. S4/5 Entry and Exit Sequence



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