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PIFE32251B-R47MS Scheda tecnica(PDF) 5 Page - Texas Instruments |
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PIFE32251B-R47MS Scheda tecnica(HTML) 5 Page - Texas Instruments |
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5 / 96 page  5 TPS65094 www.ti.com SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019 Submit Documentation Feedback Product Folder Links: TPS65094 Revision History Copyright © 2015–2019, Texas Instruments Incorporated Changes from Revision A (June 2016) to Revision B Page • Updated the PROCHOT pin description in the Pin Functions table .......................................................... 10 • Changed the values for LX3, LX4, LX5 from –1 V and 7 V to –2 V and 8 V in the Absolute Maximum Ratings table 11 • Changed the reset value of the LDOA2 VID register (LDOA2VID) to OTP dependent .................................... 62 • Added the Receiving Notification of Documentation Updates section ....................................................... 84 • Changed the Electrostatic Discharge Caution statement ...................................................................... 84 Changes from September 11, 2015 to June 2, 2016 (from * Revision (September 2015) to A Revision) Page • Released full data sheet as SWCS133A version from SWCS130B version .................................................. 1 • Changed device status to PROD_DATA .......................................................................................... 1 • Changed VIN recommended minimum ............................................................................................. 1 • Changed Features to improve description of converters ....................................................................... 1 • Changed Features to up to 400 mA of output current for load switches ...................................................... 1 • Changed functional block diagram to include TPS65094x family ............................................................. 3 • Changed the Functional Block Diagram to include an inverter on PROCHOT pin ........................................... 3 • Changed PROCHOTB to PROCHOT throughout the document ............................................................... 7 • Changed minimum absolute-maximum-rating value for SW1, SW2, and SW6 in Section 5.1 ............................ 11 • Changed VSYS in Section 5.3, Recommended Operating Conditions ...................................................... 12 • Deleted nominal value from PVINVTT in Section 5.3, Recommended Operating Conditions ........................... 12 • Deleted (nu = symbol for efficiency) ............................................................................................. 14 • Changed BUCK1 DC output voltage step size to show full range and be consistent in Section 5.7 .................... 14 • Changed typo to match correct default of 1 V for ΔVOUT_TR in Section 5.7 ................................................. 14 • Changed BUCK2 DC output voltage to show full range and be consistent in Section 5.7 ................................ 15 • Changed set condition for BUCK6 for VOUT range in Section 5.7 to match BUCK1 and BUCK2 ........................ 16 • Updated formatting and added new OTP information for BUCK6 in Section 5.7 ........................................... 16 • Updated formatting for BUCK3 DC output voltage in Section 5.8 ............................................................ 18 • Changed DC output voltage formatting for BUCK4 in Section 5.8 ........................................................... 19 • Changed maximum IOUT value for BUCK4 in Section 5.8 to match device capabilities ................................... 19 • Changed IOUT and ΔVOUT/ΔIOUT for VTT LDO in Section 5.9 for new OTPs ................................................. 24 • Changed test conditions for VTT LDO overcurrent protection in Section 5.9 ............................................... 24 • Changed Section 5.10 to show SWB1_2 RDSON is specified per output .................................................... 25 • Changed fSW values in Section 5.15 to provide more values ................................................................. 27 • Changed current to 1.9 A to match SoC requirements in Table 6-1 ......................................................... 29 • Changed BUCK6, LDOA2, LDOA3 typical output voltage range to: OTP Dependent in Table 6-1 ...................... 29 • Changed table note to include additional DDR types in Table 6-1 ........................................................... 29 • Changed PMIC Functional Block Diagram to match specifications table ................................................... 31 • Changed PROCHOTB to PROCHOT in the Apollo Lake Power Map ....................................................... 31 • Changed current ratings in Apollo Lake Power Map ........................................................................... 31 • Deleted SWBx PG from PG of PCH_PWROK in Table 6-2 ................................................................... 32 • Changed BUCK1–2 to all BUCKs and LDOAs in Section 6.3.3.3 ............................................................ 37 • Added Table 6-5 and Table 6-6 to Section 6.3.4.2 ............................................................................. 39 • Added more DDR values to the table note in Table 6-7 ....................................................................... 40 • Changed Section 6.3.5 to include LDOA1 and reset information ............................................................. 41 • Changed Section 6.6 to include multiple DDRs ................................................................................. 41 • Changed Figure 6-7 and Figure 6-8 to include alternate SWB1_2 Timing .................................................. 43 • Changed SWB1_2 from: V3P3A to: V1P8U in Table 6-10 .................................................................... 43 • Changed VDDQ voltage to OTP Dependent and SWBx to SWB1_2 in Table 6-11 ....................................... 45 • Updated Figure 6-10 to include alternate SWB1_2 Timing .................................................................... 46 • Changed Section 6.3.5.5 to include alternate SWB1_2 Timing ............................................................... 47 • Changed Section 6.3.5.6 to include THERMTRIPB ........................................................................... 48 • Added the TPS65094x family OTP values to Section 6.6 ..................................................................... 53 • Replaced VID values with link to full VID table in Table 6-18 and Table 6-19 .............................................. 56 • Updated naming of bits in the TEMPHOT register .............................................................................. 71 |
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