SM320VC33 datasheet(44/54 Pages) TI

44 / 54 page

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251-1443

data-rate timing modes

Unless otherwise indicated, the data-rate timings shown in Figure 30 and Figure 31 are valid for all serial-port

modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s

Guide (literature number SPRU031).

The serial-port timing parameters are defined in the preceding “serial-port timing parameters” tables. The

numbers shown in Figure 30 and Figure 31 correspond with those in the NO. column of each table.

FSX(EXT)

FSX(INT)

FSR

CLKX/R

Bit 0

Bit n-1

Bit n-2

Bit n-1

Bit n-2

td(H1H-SCK)

tc(SCK)

tw(SCK)

tr(SCK)

tf(SCK)

td(CLKX- DX)

tsu(DR- CLKRL)

th(CLKRL- DR)

td(CLKX- FSX)

tsu(FSR- CLKRL)

td(CLKX- FSX)

th(SCKL- FS)

tsu(FSX- CLKX)

td(CLKX- DX)V

tdis(CLKX- DXZ)

NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.

B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.

Figure 30. Fixed Data-Rate Mode Timing

CLKX/R

FSX(INT)

FSX(EXT)

FSR

Bit 0

Bit n-2

Bit n-3

Bit n-2

Bit n-3

Bit n-1

td(CLKX- FSX)

td(FSX- DX)V

tsu(FSX- CLKX)

tsu(DR- CLKRL)

td(CLKX- DX)

th(CLKRL-DR)

th(SCKL-FS)

tsu(FSR-CLKRL)

td(CLKX-DX)V

tdis(CLKX-DXZ)

NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.

B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.

C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed

data-rate mode.

Figure 31. Variable Data-Rate Mode Timing

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