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SM320VC33 Scheda tecnica(PDF) 28 Page - Texas Instruments

Il numero della parte SM320VC33
Spiegazioni elettronici  DIGITAL SIGNAL PROCESSOR
PDF  54 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

SM320VC33 Scheda tecnica(HTML) 28 Page - Texas Instruments

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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
clock circuit timing (continued)
The following tables define the timing requirements and switching characteristics for EXTCLK.
timing requirements for EXTCLK, all modes (see Figure 16 and Figure 17)
MIN
MAX
UNIT
t
Rise time EXTCLK
F = Fmax, x0.5 and x1 modes
1*
ns
tr(EXTCLK)
Rise time, EXTCLK
F < Fmax
4*
ns
t
Fall time EXTCLK
F = Fmax, x0.5 and x1 modes
1*
ns
tf(EXTCLK)
Fall time, EXTCLK
F < Fmax
4*
ns
x5 mode
21*
tw(EXTCLKL)
Pulse duration, EXTCLK low
x1 mode
6*
ns
tw(EXTCLKL)
Pulse duration, EXTCLK low
x0.5 mode
4*
ns
x5 mode
21*
tw(EXTCLKH)
Pulse duration, EXTCLK high
x1 mode
5*
ns
tw(EXTCLKH)
Pulse duration, EXTCLK high
x0.5 mode
4*
ns
x5 PLL mode
40*
60*
tdc(EXTCLK)
Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)]
x1 and x0.5 modes, F = max
45
55
%
tdc(EXTCLK)
Duty cycle, EXTCLK [tw(EXTCLKH) / tc(H)]
x1 and x0.5 modes, F = 0 Hz
0*
100*
%
x5 mode
66.7*
200*
tc(EXTCLK)
Cycle time, EXTCLK
x1 mode
13.3
ns
tc(EXTCLK)
Cycle time, EXTCLK
x0.5 mode
10*
ns
x5 mode
5*
15*
Fext
Frequency range, 1/tc(EXTCLK)
x1 mode
0
75
MHz
Fext
Frequency range, 1/tc(EXTCLK)
x0.5 mode
0*
100*
MHz
* Not production tested
switching characteristics for EXTCLK over recommended operating conditions, all modes
(see Figure 16 and Figure 17)
PARAMETER
MIN
TYP
MAX
UNIT
Vmid
Mid-level, used to measure duty cycle
0.5 x DVDD
V
t
Delay time, EXTCLK to H1 and
x1 mode
2*
4.5
7*
ns
td(EXTCLK-H)
Delay time, EXTCLK to H1 and
H3
x0.5 mode
2*
4.5
7*
ns
tr(H)
Rise time, H1 and H3
3*
ns
tf(H)
Fall time, H1 and H3
3*
ns
td(HL-HH)
Delay time, from H1 low to H3 high or from H3 low to H1 high
-1.5*
2*
ns
x5 PLL mode
1/(5 x fext)
tc(H)
Cycle time, H1 and H3
x1 mode
1/fext
ns
tc(H)
Cycle time, H1 and H3
x0.5 mode
2/fext
ns
* Not production tested



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