XRT75VL00D datasheet(81/92 Pages) EXAR

81 / 92 page

XRT75VL00D

REV. 1.0.3

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

9.7.2

Wander Measurement Test Results

Wander Measurement test results will be provided in the next revision of the LIU Data Sheet.

9.8

Designing with the LIU

In this section, we will discuss the following topics.

• How to design with and configure the LIU to permit a system to meet the above-mentioned Intrinsic Jitter and

Wander requirements.

• How is the LIU able to meet the above-mentioned requirements?

• How does the LIU permits the user to comply with the SONET APS Recovery Time requirements of 50ms

(per Telcordia GR-253-CORE)?

• How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Customer’s site?

9.8.1

How to design and configure the LIU to permit a system to meet the above-mentioned

Intrinsic Jitter and Wander requirements

As mentioned earlier, in most application (in which the LIU will be used in a SONET De-Sync Application) the

user will typically interface the LIU to a Mapper device in the manner as presented below in Figure 57.

In this application, the Mapper has the responsibility of receiving a SONET STS-N/OC-N signal and extracting

as many as N DS3 signals from this signal. As a given channel within the Mapper IC extracts out a given DS3

signal (from SONET) it will typically be applying a Clock and Data signal to the "Transmit Input" of the LIU IC.

Figure 57 presents a simple illustration as to how one channel, within the LIU should be connected to the

Mapper IC.

As mentioned above, the Mapper IC will typically output a Clock and Data signal to the LIU. In many cases,

the Mapper IC will output the contents of an entire STS-1 data-stream via the Data Signal to the LIU. However,

the Mapper IC typically only supplies a clock pulse via the Clock Signal to the LIU coincident to whenever a

DS3 bit is being output via the Data Signal. In this case, the Mapper IC would not supply a clock edge

coincident to when a TOH, POH or any non-DS3 data-bit is being output via the Data-Signal.

Figure 57 indicates that the Data Signal from the Mapper device should be connected to the TPDATA_n input

pin of the LIU IC and that the Clock Signal from the Mapper device should be connected to the TCLK_n input

pin of the LIU IC.

In this application, the LIU has the following responsibilities.

FIGURE 57. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS

DS3 to STS-N

Mapper/

Demapper

DS3 to STS-N

Mapper/

Demapper

LIU

STS-N Signal

TPDATA_n input pin

TCLK n input

De-Mapped (Gapped)

DS3 Data and Clock

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