XRT75VL00D datasheet(87/92 Pages) EXAR

87 / 92 page

XRT75VL00D

REV. 1.0.3

E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

HOW MAJOR PATTERN B IS SYNTHESIZED

MAJOR PATTERN B is created (by the Mapper IC) by:

• Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times.

• Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted

repeatedly 36 times.

• pon completion of the 35th transmission of MINOR PATTERN P2, MINOR PATTERN P3 is transmitted once.

Figure 62 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN B.

Hence, MAJOR PATTERN B consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses.

These 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 STS-1 (or 51.84MHz)

clock periods.

PUTTING THE PATTERNS TOGETHER

Finally, the DS3 to OC-N Mapper IC clock output is reproduced by doing the following.

• MAJOR PATTERN A is transmitted two times (repeatedly).

• After the second transmission of MAJOR PATTERN A, MAJOR PATTERN B is transmitted once.

• Then the whole process repeats.

Throughout the remainder of this document, we will refer to this particular pattern as the "SUPER PATTERN".

Figure 63 presents an illustration of this "SUPER PATTERN" which is output via the Mapper IC.

FIGURE 61. ILLUSTRATION OF MINOR PATTERN P3

FIGURE 62. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B

PATTERN P1

PATTERN P2

Repeats 63 Times

Repeats 35 Times

PATTERN P3

Transmitted 1 Time

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