CS4210 datasheet(45/102 Pages) NSC

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Index 34h

Capabilities Pointer Register

7:0

Capabilities Pointer

See Note

Capabilities Pointer: This register provides a pointer into the PCI configu-

ration header where the PCI power management register block resides.

The configuration header registers residing at Index 44h and 48h provide

the power management registers. The presence of this register is controlled

by the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]).

If enabled this register points to Index 44h otherwise it reads zero.

Note:

The reset value is dependent upon the PCICapabilities bit in the nscControl register (BAR1+Offset 00h[20]) which can be con-

figured by the serial EEPROM. If enabled in the EEPROM, the reset value of the register is 44h. If not enabled in the EEPROM

or if no EEPROM is present, then the reset value is 00h.

Index 35h-3Bh

Reserved

Index 3Ch

Interrupt Line Register

7:0

Interrupt Line

R/W

FFh

Interrupt Line: This register is used to identify which of the system inter-

rupt lines on the interrupt controller the CS4210 interrupt pin is routed to.

The reset value of FFh indicates no connection.

Index 3Dh

Interrupt Pin Register

7:0

Interrupt Pin

01h

Interrupt Pin: This register defines which of the four PCI interrupt request

pins this device uses. The CS4210 uses INTA#.

Index 3Eh

Min Grant Register

7:0

Min Grant

00h

Min Grant: This register specifies how many 250 ns periods are required

by the CS4210 for burst transfers. A reset value of 00h specifies no strin-

gent requirements on burst lengths.

Index 3Fh

Max Latency Register

7:0

Max Lat

00h

Max Latency: This register defines how quickly the CS4210 requires the

PCI bus after its REQ# has been asserted. The value of zero indicates

there are no stringent requirements for PCI bus latency.

Index 40h-43h

Reserved

Index 44h

Capability ID Register

7:0

CapabilityID

01h

Capability ID: This register specifies that the CS4210 supports PCI power

management. It reads zero if the Capabilities Pointer (Index 34h[7:0]) is dis-

abled. When visible, the value of 01h is the unique ID assigned to PCI

power management capability by the PCI SIG.

Index 45h

Next Item Pointer Register

7:0

NextItemPointer

00h

Next Item Pointer: This register specifies the pointer to the next capability

item. This field returns 0 indicating that only one additional capability is sup-

ported.

Table 4-6. PCI Configuration Register Definitions

Bit

Name

Access

Reset

Description

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