CS4210 datasheet(67/102 Pages) NSC

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4.4.12.2 programPhyEnable and aPhyEnhanceEnable

After a hardware or software reset, system software must

ensure that the CS4210 and the CS4103 are set to a con-

sistent, compatible set of P1394a enhancements. The pro-

gramPhyEnable

and

aPhyEnhanceEnable

bits

are

provided to enable software to accomplish this task. Since

different levels of software may be responsible for ensuring

this setup, the programPhyEnable bit is defined to allow

communication between implementation specific lower-

level software (e.g., BIOS or Open Firmware) and generic,

implementation independent upper-level software (e.g.,

OHCI device driver). If generic software reads this bit as a

1, it is responsible for configuring the P1394a enhance-

ments in both the CS4210 and CS4103 in a consistent

manner (either all enhancements enabled or all enhance-

ments disabled). A 0 value for this bit informs the upper-

level system software that no further changes to the

P1394a configurations of the CS4210 and CS4103 are per-

mitted since either:

Lower-level software has previously performed initial-

ization appropriate to the CS4210 capabilities, or

The link has hardwired P1394a capabilities to match

the CS4103. Note that this bit is only a software flag

and does not control any CS4210 functionality.

The programPhyEnable bit may be read-only, returning a

zero value, if upper-level software is not involved in the

configuration of P1394a enhancements for the CS4210

and CS4103. This is appropriate when the CS4210 and

CS4103 are hardwired with compatible settings or when

lower-level software consistently configures both the

CS4210 and CS4103. To allow the possibility for upper-

level software control of P1394a enhancements, program-

PhyEnable should be implemented as read/clear with a

hardware reset value of 1. Software should clear program-

PhyEnable once the CS4210 and CS4103 have been pro-

grammed consistently by either lower-level or upper-level

software. When programPhyEnable is set to 1, the aPhy-

EnhanceEnable bit allows generic software to enable or

disable all P1394a enhancements within the CS4210 Link.

A value of 1 for aPhyEnhanceEnable configures the Link to

use all P1394a enhancements and is appropriate when

software has enabled all of the enhancements within the

CS4103. Likewise, a value of 0 prevents the Link from

using any P1394a enhancements and is appropriate when

software has disabled all of the enhancements within the

CS4103. Note that generic software must not attempt to

modify or interpret the setting of the aPhyEnhanceEnable

bit if programPhyEnable contains a 0. The aPhyEnhan-

ceEnable bit is read/set/clear and it resets to 0 for default

compatibility with legacy PHYs. These bits are accessible

from the nscControl register (BAR1+Offset 00h[14,13]).

The aPhyEnhanceEnable bit can be initialized with the

serial EEPROM.

4.4.12.3 LPS and linkEnable

There are three basic tasks and ensuing requirements with

respect to the Phy-Link interface:

Bootstrap of Open HCI.

This requires a mechanism to configure the CS4210

and CS4103 prior to receiving any packets or generat-

ing any bus requests.

Recovery from a hung system.

This requires a mechanism which places OpenHCI in

a near pre-bootstrap condition, and allows the CS4210

and CS4103 to get back into sync if required.

Power Management via Suspend/Resume

This requires a mechanism to inform the CS4103 that

Phy-Link communication is no longer required and the

CS4103 can suspend itself if no active ports remain.

To achieve proper behavior in satisfying these require-

ments, software shall always assert the signals in the fol-

lowing sequence: LPS, then linkEnable, then any other

individual context enables or runs. The CS4210 behavior

when violating this order is undefined and can produce

unreliable behavior. Table 4-22 illustrates the progressive

functionality as these signals are asserted.

Following a hardware or software reset, LPS and linkEn-

able areOff as showninStepa(in Table4-22). Software

proceeds to enable the link power status (b) and when

SCLK has started, software can configure the CS4210 and

CS4103 registers as listed in Step c (e.g., Self-ID receive

DMA registers). Setting linkEnable in step d enables some

DMA function, and asserting contextControl.run (e) for the

CS4210 contexts then yields full functionality

Table 4-22. LPS and linkEnable Assertion

Step

LPS

(BAR0+Offset 50h[19])

linkEnable

(BAR0+Offset 50h[17])

contextControl.run

Sequence Comments

Off

Initial State

Off

Allows SCLK to start

Off

Config Phy-Link registers

Off

Initiate Bus Reset

Off

Physical DMA/Cycle Starts

Okay

Normal Operation

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