CS4210 datasheet(14/102 Pages) NSC

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Revision 1.0

Signal Definitions (Continued)

2.2.3

Miscellaneous Interface Signals

Signal Name

Pin No.

Type

Description

EECLK

Serial EEPROM Clock

The I2C bus clock signal.

EEDATA

Serial EEPROM Data

The I2C data signal.

CCLKO

Cycle Clock Output

The 8 kHz reference clock output.

CCLKI

Cycle Clock Input

The 8 kHz reference clock input.

CMC

Contender Master Control

This output is set via the nscCMCControl.CMC bit (BAR1+Offset 18h[0]).

The value placed on the bit is directly reflected on this pin.

CMCL

Contender Master Control Link Enabled

This output is set via the nscCMCControl.CMCL bit (BAR1+Offset 18h[1]).

The value of the bit is reflected on the output when HCControl.linkEnable

(BAR0+Offset 50h[17]) is set. Otherwise it is 0.

TESTO

Test Out

National internal test pin, user must float.

TESTEN#

Test Enable

National internal test pin, user must tie high.

2.2.4

Power Supplies and Ground Connections

Signal Name

Pin No.

Type

Description

VDD

9, 13, 20, 35, 46, 55,

70, 80, 91, 96

PWR

2.5V Core Power Supply Connections (Total of 10)

VDDIO

6, 16, 39, 63, 87

PWR

3.3V I/O Power Supply Connections (Total of 5)

VSS

1, 11, 24, 30, 42, 50,

60, 75, 83, 94, 100

GND

Ground Connections (Total of 11)

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