R7FA2L1AB2DFM datasheet(41/110 Pages) RENESAS

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tIRQW

IRQ

Figure 2.13

IRQ interrupt input timing

2.3.6

I/O Ports, POEG, GPT, AGT, KINT, and ADC12 Trigger Timing

Table 2.27

I/O Ports, POEG, GPT, AGT, KINT, and ADC12 trigger timing

Parameter

Symbol

Min

Max

Unit

Test

conditions

I/O Ports

Input data pulse width

2.7 V ≤ VCC ≤ 5.5 V

tPRW

—

tPcyc

Figure 2.14

2.4 V ≤ VCC < 2.7 V

1.6 V ≤ VCC < 2.4 V

POEG

POEG input trigger pulse width

tPOEW

—

tPcyc

Figure 2.15

GPT

Input capture pulse width

Single edge

tGTICW

1.5

—

tPDcyc

Figure 2.16

Dual edge

2.5

—

AGT

AGTIO, AGTEE input cycle

1.8 V ≤ VCC ≤ 5.5 V

tACYC*1

250

—

Figure 2.17

1.6 V ≤ VCC < 1.8 V

2000

—

AGTIO, AGTEE input high-level

width, low-level width

1.8 V ≤ VCC ≤ 5.5 V

tACKWH,

tACKWL

100

—

1.6 V ≤ VCC < 1.8 V

800

—

AGTIO, AGTO, AGTOA,

AGTOB output cycle

2.7 V ≤ VCC ≤ 5.5 V

tACYC2

62.5

—

Figure 2.17

2.4 V ≤ VCC < 2.7 V

125

—

1.8 V ≤ VCC < 2.4 V

250

—

1.6 V ≤ VCC < 1.8 V

500

—

ADC12

12-bit A/D converter trigger input pulse width

tTRGW

1.5

—

tPcyc

Figure 2.18

KINT

KRn (n = 00 to 07) pulse width

tKR

250

—

Figure 2.19

Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.

Port

tPRW

Figure 2.14

I/O ports input timing

RA2L1 Datasheet

2. Electrical Characteristics

R01DS0385EJ0100 Rev.1.00

Aug 06, 2020

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