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R7FA2L1AB2DFM Scheda tecnica(PDF) 6 Page - Renesas Technology Corp |
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R7FA2L1AB2DFM Scheda tecnica(HTML) 6 Page - Renesas Technology Corp |
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6 / 110 page ![]() 1.2 Block Diagram Figure 1.1 shows a block diagram of the MCU superset. Some individual devices within the group have a subset of the features. Memory 256-KB code flash 8-KB data flash 32-KB SRAM DMA System Mode control Power control ICU MOSC/SOSC Clocks (H/M/L) OCO GPT32 × 4 GPT16 × 6 Timers AGT × 2 RTC CTSU KINT Arm Cortex-M23 NVIC System timer Test and DBG Interface DTC WDT/IWDT CAC POR/LVD Reset Human machine interfaces ELC Event link AES + TRNG Security Analogs CRC Data processing DOC Communication interfaces IIC × 2 SPI × 2 SCI × 5 TSN DAC12 × 1 ACMPLP × 2 ADC12 MPU Bus MPU Register write protection CAN × 1 Figure 1.1 Block diagram 1.3 Part Numbering Figure 1.2 shows the product part number information, including memory capacity and package type. Table 1.11 shows a list of products. RA2L1 Datasheet 1. Overview R01DS0385EJ0100 Rev.1.00 Aug 06, 2020 Page 6 of 110 |
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