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R5F572TFGDFP Scheda tecnica(PDF) 52 Page - Renesas Technology Corp

Il numero della parte R5F572TFGDFP
Spiegazioni elettronici  Maximum operating frequency: 200 MHz Capable of 1160 CoreMark in operation at 200 MHz
PDF  176 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F572TFGDFP Scheda tecnica(HTML) 52 Page - Renesas Technology Corp

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R01DS0331EJ0100 Rev.1.00
Page 52 of 176
Feb 08, 2019
RX72T Group
3. Address Space
3.
Address Space
3.1
Address Space
This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh.
Figure 3.1 shows the memory maps in the respective operating modes. Accessible areas will differ according to the
operating mode and states of control bits.
Figure 3.1
Memory Map in Each Operating Mode
Reserved area*3
Reserved area*3
Reserved area*3
Reserved area*3
Reserved area*3
Reserved area*3
External address space
(CS area)
Reserved area*3
External address space
(CS area)
RAM*2
ROM (code flash memory)*
2
ROM (data flash memory)*2
External address space
(CS area)
0000 0000h
0008 0000h
FFFF FFFFh
Single-chip mode*1
RAM*2
ROM (code flash memory)*
2
0010 0000h
0010 8000h
ROM (data flash memory)*2
0100 0000h
ECCRAM
FFF0 0000h
ROM (user boot)
0000 0000h
0008 0000h
On-chip ROM enabled
extended mode
0010 0000h
0100 0000h
0800 0000h
0000 0000h
0008 0000h
FFFF FFFFh
On-chip ROM disabled
extended mode
0010 0000h
0100 0000h
0800 0000h
FF00 0000h
00FF C000h
00FF C000h
FF7F 8000h
FF80 0000h
ROM (user boot)
ECCRAM
0010 8000h
FFFF FFFFh
FFF0 0000h
FF7F 8000h
FF80 0000h
ECCRAM
00FF C000h
ROM (option-setting memory)
0012 0040h
Reserved area*3
0012 0080h
007E 0000h
Reserved area*3
Peripheral I/O register
0080 0000h
Reserved area*3
ROM (option-setting memory)
0012 0040h
Reserved area*3
0012 0080h
007E 0000h
Reserved area*3
Peripheral I/O register
0080 0000h
Peripheral I/O register
Reserved area*3
000A 4000h
Peripheral I/O register
000A 6000h
Peripheral I/O register
000A 4000h
Peripheral I/O register
000A 6000h
000A 4000h
000A 6000h
Reserved area*3
Reserved area*3
Reserved area*3
Reserved area*3
Reserved area*3
0002 0000h
0002 0000h
0500 0000h
0002 0000h
0500 0000h
RAM*2
Peripheral I/O register
Peripheral I/O register
Reserved area*3
Reserved area*3
Note 1. The memory map in boot mode and user boot mode is the same as that in single-chip mode.
Note 2. The capacity of ROM differs depending on the products.
Note 3. Reserved areas should not be accessed.
Code Flash Memory
Data Flash Memory
RAM
Capacity
Address
Capacity
Address
Capacity
Address
1 Mbyte
FFF0 0000h to FFFF FFFFh
32 Kbytes
0010 0000h to 0010 7FFFh
128 Kbytes
0000 0000h to 0001 FFFFh
512 Kbytes
FFF8 0000h to FFFF FFFFh



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