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R5F572TFGDFP Scheda tecnica(PDF) 90 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 90 Page - Renesas Technology Corp |
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90 / 176 page  R01DS0331EJ0100 Rev.1.00 Page 90 of 176 Feb 08, 2019 RX72T Group 4. I/O Registers 000A 0098h USB0 Pipe3 Transaction Counter Enable Register PIPE3TRE 16 16 9 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 009Ah USB0 Pipe3 Transaction Counter Register PIPE3TRN 16 16 9 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 009Ch USB0 Pipe4 Transaction Counter Enable Register PIPE4TRE 16 16 9 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 009Eh USB0 Pipe4 Transaction Counter Register PIPE4TRN 16 16 9 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00A0h USB0 Pipe5 Transaction Counter Enable Register PIPE5TRE 16 16 9 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00A2h USB0 Pipe5 Transaction Counter Register PIPE5TRN 16 16 9 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00D0h USB0 Device Address 0 Configuration Register DEVADD0 16 169 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00D2h USB0 Device Address 1 Configuration Register DEVADD1 16 169 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00D4h USB0 Device Address 2 Configuration Register DEVADD2 16 169 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00D6h USB0 Device Address 3 Configuration Register DEVADD3 16 169 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00D8h USB0 Device Address 4 Configuration Register DEVADD4 16 169 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00DAh USB0 Device Address 5 Configuration Register DEVADD5 16 169 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 00F0h USB0 PHY Cross Point Adjustment Register PHYSLEW 32 32 9 PCLKB or more Frequency with 1 + 9 × (frequency ratio of ICLK/ PCLKB)*1 USBb 000A 0C80h CMPC0 Comparator Control Register CMPCTL 8 8 1, 2 PCLKB 1, 2 ICLK CMPC 000A 0C84h CMPC0 Comparator Input Select Register CMPSEL0 8 8 1, 2 PCLKB 1, 2 ICLK CMPC 000A 0C88h CMPC0 Comparator Reference Voltage Select Register CMPSEL1 8 8 1, 2 PCLKB 1, 2 ICLK CMPC 000A 0C8Ch CMPC0 Comparator Output Monitor Register CMPMON 8 8 1, 2 PCLKB 1, 2 ICLK CMPC 000A 0C90h CMPC0 Comparator External Output Enable Register CMPIOC 8 8 1, 2 PCLKB 1, 2 ICLK CMPC 000A 0CA0h CMPC1 Comparator Control Register CMPCTL 8 8 1, 2 PCLKB 1, 2 ICLK CMPC 000A 0CA4h CMPC1 Comparator Input Select Register CMPSEL0 8 8 1, 2 PCLKB 1, 2 ICLK CMPC Table 4.1 List of I/O Registers (Address Order) (35 / 54) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles Related Function ICLK ≥ PCLK ICLK < PCLK |
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