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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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R5F572TFGDFP Scheda tecnica(PDF) 130 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 130 Page - Renesas Technology Corp |
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130 / 176 page  R01DS0331EJ0100 Rev.1.00 Page 130 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics 5.4.5 Bus Timing Table 5.24 Bus Timing (1) Conditions: 4.5 V ≤ VCC ≤ 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65). Item Symbol Min. Typ. Max. Unit Test Conditions Address delay time tAD — — 12.5 ns Figure 5.16 to Figure 5.21 Byte control delay time tBCD — — 12.5 CS# delay time tCSD — — 12.5 ALE delay time tALED — — 12.5 RD# delay time tRSD — — 12.5 Read data setup time tRDS 12.5 — — Read data hold time tRDH 0— — WR# delay time tWRD — — 12.5 Write data delay time tWDD — — 12.5 Write data hold time tWDH 0— — WAIT# setup time tWTS 12.5 — — Figure 5.22 WAIT# hold time tWTH 0— — Table 5.25 Bus Timing (2) Conditions: 2.7 V ≤ VCC < 4.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65). Item Symbol Min. Typ. Max. Unit Test Conditions Address delay time tAD — — 25 ns Figure 5.16 to Figure 5.21 Byte control delay time tBCD —— 25 CS# delay time tCSD —— 25 ALE delay time tALED —— 25 RD# delay time tRSD —— 25 Read data setup time tRDS 25 — — Read data hold time tRDH 0— — WR# delay time tWRD —— 25 Write data delay time tWDD —— 25 Write data hold time tWDH 0— — WAIT# setup time tWTS 25 — — Figure 5.22 WAIT# hold time tWTH 0— — |
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