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VR4102 Scheda tecnica(PDF) 201 Page - NEC

Il numero della parte VR4102
Spiegazioni elettronici  64/32-bit Microprocessor
PDF  701 Pages
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Produttore elettronici  NEC [NEC]
Homepage  http://www.nec.com/
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VR4102 Scheda tecnica(HTML) 201 Page - NEC

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CHAPTER 7 INITIALIZATION INTERFACE
201
7.1.2 RSTSW
After the RSTSW# pin becomes active and then becomes inactive 100
Ps later, the VR4102 starts PLL oscillation
and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL
oscillation).
A reset by RSTSW initializes the entire internal state except for the RTC timer and the PMU. Since the DRAM is
not switched to self refresh mode, the contents of DRAM after an RTC reset are not at all guaranteed.
After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to
access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the
VR4102, the processor should be completely initialized by software.
Figure 7-2. RSTSW
H
L
Reset#(internal)
ColdReset#(internal
MPOWER(o)
POWER(i)
RTC
(internal, 32kHz)
Stable oscillation
16MasterClock
Note
16ms
>3RTC
PLL(internal)
Undefined
RSTSW#(i)
MRAS(0:3)#(o)
UCAS#/LCAS#(o)
Stable oscillation
Stable oscillation
Note MasterClock is the basic clock used in the CPU core.



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