PIMXRT406LCAE4A datasheet(4/100 Pages) NXP

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i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

i.MX RT1020 introduction

•

GPC hardware power management controller

The i.MX RT1020 processors support the following system debug:

•

Arm CortexM7 CoreSight debug and trace architecture

•

Trace Port Interface Unit (TPIU) to support off-chip real-time trace

•

Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse

Security functions are enabled and accelerated by the following hardware:

•

High Assurance Boot (HAB)

•

Data Co-Processor (DCP):

— AES-128, ECB, and CBC mode

— SHA-1 and SHA-256

— CRC-32

•

Bus Encryption Engine (BEE)

— AES-128, ECB, and CTR mode

— On-the-fly QSPI Flash decryption

•

True random number generation (TRNG)

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Secure Non-Volatile Storage (SNVS)

— Secure real-time clock (RTC)

— Zero Master Key (ZMK)

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Secure JTAG Controller (SJC)

Table 1 demonstrates the comparison between 100 LQFP and 144 LQFP package.

Table 1. The comparison between 100 LQFP and 144 LQFP package

144 LQFP

100 LQFP

RAM/KB

256

USB OTG

ENET port

MII/RMII

RMII

KPP number

8 x 8

4 x 4

SEMC

Yes

SPDIF

Yes

uSDHC1

FlexIO

GPIO

FlexPWM Channel

XBAR IN/OUT

SAI

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