PIMXRT406LCAE4A datasheet(64/100 Pages) NXP

64 / 100 page

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

Electrical characteristics

4.8.3

Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC) AC

timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single

Data Rate) timing, eMMC4.4/4.41/4.5 (Dual Date Rate) timing and SDR104/50(SD3.0) timing.

4.8.3.1

SD/eMMC4.3 (single data rate) AC timing

Figure 39 depicts the timing of SD/eMMC4.3, and Table 56 lists the SD/eMMC4.3 timing characteristics.

Figure 39. SD/eMMC4.3 timing

Table 56. SD/eMMC4.3 interface timing specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP1

400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP2

025/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP3

020/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

7—

SD3

Clock High Time

tWH

7—

SD4

Clock Rise Time

tTLH

—3

SD5

Clock Fall Time

tTHL

—3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6

uSDHC Output Delay

tOD

-6.6

3.6

SD1

SD3

SD5

SD4

SD7

SDx_CLK

SD2

SD8

SD6

Output from uSDHC to card

Input from card to uSDHC

SDx_DATA[7:0]

PIMXRT406LCAE4A Scheda tecnica(PDF) 64 Page - NXP Semiconductors

PIMXRT406LCAE4A Scheda tecnica(HTML) 64 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Scheda tecnica Scarica

Link URL