ZL30262LDF1 datasheet(38/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

OCEN1

Output Clock Enable Register 1

05h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OC8EN

OC7EN

OC6EN

OC5EN

OC4EN

OC3EN

OC2EN

OC1EN

Default

Bits 7 to 0: Output Clock x Enable (OCxEN). Each of these bits enables and disables the corresponding output

dividers, phase adjustment/alignment circuitry and start/stop circuitry. See section 5.6.1.

0 = Disabled

1 = Enabled

Note: On Rev A devices at least one OCxEN bit must be set for each of the six output banks for proper operation.

These bits should be set at or near the beginning of the configuration sequence.

OCEN2

Output Clock Enable Register 2

06h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

OC10EN

OC9EN

Default

See the OCEN1 register description above.

OCMUX1

Output Clock Mux Register 1

07h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OCMUXC

OCMUXB

OCMUXA

Default

Bits 5 to 4: Output Clock Mux C (OCMUXC[1:0]). Controls the high speed output mux for output group C (OC4

and OC5).

00 = APLL Integer divider

01 = APLL Fractional divider or bypass path (specified by ACR1.BYPASS)

10 = {unused value}

11 = Path 2 (see block diagram in Figure 1)

Bits 3 to 2: Output Clock Mux B (OCMUXB[1:0]). Controls the high speed output mux for output group B (OC3).

00 = APLL Integer divider

01 = APLL Fractional divider or bypass path (specified by ACR1.BYPASS)

10 = {unused value}

11 = Path 2 (see block diagram in Figure 1)

Bits 1 to 0: Output Clock Mux A (OCMUXA[1:0]). Controls the high speed output mux for output group A (OC1

and OC2).

00 = APLL Integer divider

01 = APLL Fractional divider or bypass path (specified by ACR1.BYPASS)

10 = {unused value}

11 = Path 2 (see block diagram in Figure 1)

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