ZL30262LDF1 datasheet(46/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

ICISR

Input Clock Interrupt Status Register

44h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

IC3

IC2

IC1

Default

Bit 3: XA Input Interrupt Status (XA). This bit indicates the current status of the interrupt sources for XA. This bit

is set when latched status XASR.XAL is set and the associated interrupt enable bit is also set. See section 5.8.

Bit 2 to 0: Input Clock x Interrupt Status (IC[3:1]). Each bit indicates the current status of the interrupt sources for

the corresponding input. It is set when latched status ICxSR.ICVL is set and the associated interrupt enable bit is

also set. See section 5.8.

OCISR1

Output Clock Interrupt Status Register 1

45h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OC8

OC7

OC6

OC5

OC4

OC3

OC2

OC1

Default

Bits 7 to 0: Output Clock x Interrupt Status (OC[8:1]). Each bit indicates the current status of the interrupt sources

for the corresponding output. It is set when any latched status bit in the OCxSR register is set and the associated

interrupt enable bit is also set. See section 5.8.

OCISR2

Output Clock Interrupt Status Register 2

46h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

OC10

OC9

Default

See the OCISR1 register description above.

APLLISR

APLL Interrupt Status Register

47h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

—

APLL

Default

Bit 0: APLL Interrupt Status (APLL). This bit indicates the current status of the interrupt sources for the APLL. It is

set when any latched status bit in the APLLSR register is set and the associated interrupt enable bit is also set. See

section 5.8.

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