ZL30262LDF1 datasheet(61/94 Pages) MICROCHIP

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ZL30260-ZL30263

Data Sheet

DS20006554A

F1CR1

APLL Fractional Output Divider Control Register 1

140h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

MODE[3:0]

—

FDL[2:0]

Default

Bits 7 to 4: APLL Fractional Output Divider Mode (MODE[3:0]).

0000 = Normal, divider-only operation

0001 = NCO or spread-spectrum operation

Other values reserved

Bits 2 to 0: APLL Fractional Output Divider Write Length (FDL[2:0]). This field indicates the last register to write

of the FDIV

multiregister field where “last register” is as described in section 6.1.3. The number of the last register to

write is FDL+1. Changing this field from its default value can be useful in NCO mode to reduce SPI or I2C bus usage

when NCO changes only affect the least significant bytes of FDIV.

F1DIV1

APLL Fractional Output Divider Register 1

141h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

FDIV[7:0]

Default

Bits 7 to 0: Fractional Output Divider Value (FDIV[7:0]). The full 40-bit FDIV[39:0] field spans the F1DIV1 through

F1DIV5 registers. FDIV is an unsigned number with 4 integer bits (FDIV[39:36]) and up to 36 fractional bits. FDIV

specifies the fixed-point term of the fractional output divider value. The value FDIV=0 is undefined. Unused least

significant bits must be written with 0. See section 5.5.5.

F1DIV2

APLL Fractional Output Divider Register 2

142h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

FDIV[15:8]

Default

Bits 7 to 0: Fractional Output Divider Value (FDIV[15:8]). See the F1DIV1 register description.

F1DIV3

APLL Fractional Output Divider Register 3

143h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

FDIV[23:16]

Default

Bits 7 to 0: Fractional Output Divider Value (FDIV[23:16]). See the F1DIV1 register description.

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