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ZL30262LDF1 Scheda tecnica(PDF) 58 Page - Microchip Technology

Il numero della parte ZL30262LDF1
Spiegazioni elettronici  1-APLL, 6- or 10-Output Any-to-Any Clock Multiplier and Frequency Synthesizer
PDF  94 Pages
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Produttore elettronici  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ZL30262LDF1 Scheda tecnica(HTML) 58 Page - Microchip Technology

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ZL30260-ZL30263
Data Sheet
58
© 2021 Microchip Technology Inc.
DS20006554A
Register Name:
AFBBP
Register Description:
APLL Feedback Divider Truncate Bit Position
Register Address:
114h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AFBBP[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: APLL Feedback Divider Truncate Bit Position (AFBBP[7:0]). This unsigned integer specifies the
number of fractional bits that are valid in the AFBDIV value. There are 33 fractional bits in AFBDIV. The value in this
AFBBP field specifies 33
– number_of_valid_AFBDIV_fractional_bits. When AFBBP=0 all 33 AFBDIV fractional bits
are valid. When AFBBP=9, the most significant 24 AFBDIV fractional bits are valid and the least significant 9 bits
must be set to 0. This register field is only used when the feedback divider value is expressed in the form AFBDIV +
AFBREM / AFBDEN. AFBBP values greater than 33 are invalid. See section 5.5.4.
Register Name:
AIDCR
Register Description:
APLL Frequency Increment-Decrement Configuration Register
Register Address:
115h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DECF
FDSS[2:0]
INCF
FISS[2:0]
Default
0
0
0
0
0
0
0
0
Bit 7: Decrement Frequency (DECF). When FDSS=000, this bit is the APLL frequency decrement control signal.
See section 5.5.7.
Bits 6 to 4: Frequency Decrement Source Select (FDSS[2:0]). This field specifies the APLL frequency decrement
control signal. Every low-to-high transition and every high-to-
low transition of the signal decrements the APLL’s
output frequency by the amount specified by AID[23:0] x 27. See section 5.5.7.
000 = DECF bit
001 = GPIO0
010 = GPIO1
011 = GPIO2
100 = GPIO3
101 to 111 = {unused values}
Bit 3: Increment Frequency (INCF). When FISS=000, this bit is the APLL frequency increment control signal. See
section 5.5.7.
Bits 2 to 0: Frequency Increment Source Select (FISS[2:0]). This field specifies the APLL frequency increment
control signal. Every low-to-high transition and every high-to-low
transition of the signal increments the APLL’s output
frequency by the amount specified by AID[23:0] x 27. See section 5.5.7.
000 = INCF bit
001 = GPIO0
010 = GPIO1
011 = GPIO2
100 = GPIO3
101 to 111 = {unused values}



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