ADL6316ACCZ-R7 datasheet(35/37 Pages) AD

35 / 37 page

Data Sheet

ADL6316

Rev. 0 | Page 35 of 37

Address: 0x127, Reset: 0x00, Name: ADC_CONTROL

ADC Clock Frequency Division Ratio. Divided

Down Gated Clock

ADC Clock Divider Enable

ADC Clock Source Selection

[7:6] RESERVED

[2:0] ADC_CLK_FREQ (R/W)

[5] ADC_CLOCK_DIV_EN (R/W)

[3] RESERVED

[4] ADC_MUX_SEL (R/W)

Table 53. Bit Descriptions for ADC_CONTROL

Bits

Bit Name

Description

Reset

Access

[7:6]

RESERVED

Reserved.

0x0

ADC_CLOCK_DIV_EN

ADC Clock Divider Enable.

0x0

R/W

0: Disable ADC clock divider.

1: Enable ADC clock divider.

ADC_MUX_SEL

ADC Clock Source Selection.

0x0

R/W

0: ADC clock from SCLK.

1: Not used.

RESERVED

Reserved.

0x0

[2:0]

ADC_CLK_FREQ

ADC Clock Frequency Division Ratio. Divided Down Gated Clock.

0x0

R/W

000: ADC clock at SCLK/2.

001: ADC clock at SCLK/1.

010: ADC clock at SCLK/2.

011: ADC clock at SCLK/4.

Address: 0x128, Reset: 0x00, Name: ADC_EOC

ADC End of Conversion (EOC)

[7:1] RESERVED

[0] ADC_EOC (R)

Table 54. Bit Descriptions for ADC_EOC

Bits

Bit Name

Description

Reset

Access

[7:1]

RESERVED

Reserved

0x0

ADC_EOC

ADC End of Conversion (EOC)

0x0

Address: 0x129, Reset: 0x00, Name: ADC_OUT

Temperature Sensor Output of Auxiliary MUX

ADC

[7:0] TEMP_ADC_OUT (R)

Table 55. Bit Descriptions for ADC_OUT

Bits

Bit Name

Description

Reset

Access

[7:0]

TEMP_ADC_OUT

Temperature Sensor Output of Auxiliary Mux ADC

0x0

Address: 0x146, Reset: 0x00, Name: GENERIC_READBACK_2

VVA Attenuation Setting Readback

[7:0] VVA_ATTEN_RDBK[7:0] (R)

Table 56. Bit Descriptions for GENERIC_READBACK_2

Bits

Bit Name

Description

Reset

Access

[7:0]

VVA_ATTEN_RDBK[7:0]

VVA Attenuation Setting Readback

0x0

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