| Motore di ricerca datesheet componenti elettronici |
|
ADL6316ACCZ-R7 Scheda tecnica(PDF) 19 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADL6316ACCZ-R7 Scheda tecnica(HTML) 19 Page - Analog Devices |
|
19 / 37 page ![]() Data Sheet ADL6316 Rev. 0 | Page 19 of 37 DEVICE SETUP The recommended sequence of steps to set up the ADL6316 is as follows: 1. Set up the SPI interface. See Table 13. 2. Set up the common parameters, including auxiliary mux control. See Table 14 and Table 15. 3. Set up the operating mode. See Table 16 to Table 19. a. Set the attenuation on the DSA. b. Enable or disable the amplifiers. c. Set the amplifier reference currents. d. Set the amplifier for linearity optimization. e. Measure the internal temperature. Table 13. SPI Interface Setup Address Setting Notes 0x000 0x99 Soft reset, MSB first, SDO active (4-wire SPI) 0x001 0x00 Single instruction, master/slave readback, soft reset, and master/slave transfer 0x00A 0x00 Scratch pad Table 14. Signal Path Trim Address Setting Description 0x100 0xFF Enable the DAC, auxiliary mux band gap, ADC, bias generator, DSA, and VVA 0x101 0x01 Enable IP3 optimization and 3.3 V LDO regulator 0x106 0x00 Disable the bias current, IBIAS, via the EN_IBIASGEN_RESISTOR bit (default setting) 0x105 0x00 VVA control source from DAC 0x104 0x0F Attenuation of VVA at minimum attenuation, highest four bits of 12-bit word 0x103 0xFF Attenuation of VVA at minimum attenuation, lowest eight bits of 12-bit word Table 15. Auxiliary Mux Control Address Setting Description 0x120 0x00 PTAT to ADC input, PTAT on mux output 0x121 0x00 Set SPI SDO voltage to 1.8 V Table 16. Power-Down Mode Setup, TXEN = Logic Level 0 Address Setting Description 0x102 0x1F 14 dB attenuation on DSA 0x107 0x80 Set Amplifier 1 reference current, IREF (TRM_AMP1_IREF_0), for low power mode 0x108 0x80 Disable Amplifier 1 0x109 0x80 Set Amplifier 2 IREF (TRM_AMP2_IREF_0) for low power mode 0x10A 0x80 Disable Amplifier 2 Table 17. Normal Operating Mode Setup, TXEN = Logic Level 1 Address Setting Description 0x112 0x00 0 dB attenuation on DSA 0x117 0x82 Set Amplifier 1 IREF (TRM_AMP1_IREF_1) 0x118 0x81 Enable Amplifier 1 0x119 0x82 Set Amplifier 2 IREF (TRM_AMP2_IREF_1) 0x11A 0x81 Enable Amplifier 2 Table 18. Linearity Optimization Address Setting Description 0x10B 0x02 Set the TRM_AMP2_CB bit 0x11B 0x02 Set the TRM_AMP2_IP3 bit |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |