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SP9841 Scheda tecnica(PDF) 16 Page - Sipex Corporation |
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SP9841 Scheda tecnica(HTML) 16 Page - Sipex Corporation |
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16 / 32 page ![]() 282 Pin 10 — V OUTG — DACG Voltage Output. Pin 11 — V OUTH — DACH Voltage Output. Pin 12 — V ING/H — DACG and H Reference Voltage Input. Pin 13 — LOADH — Load DAC Register Strobe; active high input that transfers the data bits from the Serial Input Register into the decoded DAC Register. Refer to Table 1. Pin 14 — CLOCK — Serial Clock Input; positive– edge triggered. Pin 15 — SDO — Serial Data Output; active totem– pole output. Pin 16 — GND — Ground. Pin 17 — SDI — Serial Data Input. Pin 18 — V DD — Positive 5V Power Supply. Pin 19 — V INC/D — DACC and D Reference Voltage Input. Pin 20 — V OUTD — DACD Voltage Output. FEATURES… The SP9841 and SP9842 include eight separate op amp–buffered eight–bit DACs. These can be used to replace up to eight trimpots with eight low–imped- ance programmable sources. The SP9841 uses eight separate multiplying reference inputs, while the SP9842 provides four pair of multiplying inputs. All of the reference inputs, in either case, are returned to acommonvoltagereferencelowpin.Theinherent2X gain from the two–quadrant multiplying reference inputs to the outputs allows the use of AC or DC multiplying reference inputs generated from a single, low supply voltage. Each DAC has its own data register which holds its output state. These data registers are updated from an internalserial-to-parallelshiftregisterwhichisloaded from a standard 3-wire serial input digital interface. Twelve data bits make up the data word clocked into the serial input register. This data word is decoded such that the first 4 bits determine the address of the DAC register to be loaded and the last 8 bits are the data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in mul- Table 1. Serial Input Decoded Truth Table LAST D0 LSB DATA ADDRESS D1 D2 D3 D4 D5 D6 D7 MSB D7 D6 D5 D4 D3 D2 D1 D0 DAC Output Voltage VOUT = D/128 (VIN – VREFL) + VREF L VREFL 1/128 (VIN – VREFL) + VREF L 127/128 (VIN – VREFL) + VREF L VIN (Preset Value) 129/128 (VIN – VREFL) + VREF L 254/128 (VIN – VREFL) + VREF L 255/128 (VIN – VREFL) + VREF L A0 LSB A1 A2 A3 MSB A3 A2 A1 A0 DAC Updated FIRST 0 0 0 0 0 0 0 0 1 1 . . 1 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 . . . 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 . . 1 0 0 1 1 0 0 1 1 0 0 . . 1 0 1 0 1 0 1 0 1 0 1 . . 1 No Operation DACA DACB DACC DACD DACE DACF DACG DACH No Operation . . No operation . . . . . . . . . |
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