SP9841 datasheet(20/32 Pages) SIPEX

20 / 32 page

286

Figure 4. Timing.

CHARACTERISTICS

(Typical @ 25

°C with V

DD = +5V unless otherwise noted.)

PARAMETER

MIN.

TYP.

MAX.

UNIT

CONDITIONS

Input Clock Pulse Width (t

CH, tCL)50

Data Setup Time (t

DS)30

Data Hold Time (t

DH)20

CLK to SDO Propagation Delay (t

PD)

100

DAC Register Load Pulse Width (t

LD)50

Preset Pulse Width (t

PR)50

Clock Edge to Load Time (t

CKLD)30

Load Edge to Next Clock Edge(t

LDCK)60

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDI

CLOCK

LOAD

VOUT

(FFH)

(08H)

SERIAL

DATA IN

SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; VIN(X) = 1.5V; VREFL = 0V)

SERIAL

DATA OUT

CLOCK

LOAD

VOUT

tDS

tCH

tCL

tLD

tLDCK

±1 LSB

ERROR BAND

tCLKD

tPD

tDH

AX or DX

PRESET

tPR

±1 LSB

ERROR BAND

(FFH)

(08H)

VOUT

Table 2. Logic Control Input Truth Table.

SDI

CLK

LOADH

PRESETL

LOGIC OPERATION

No Change

Data

Shift In One Bit from SDI

Shift Out 12–clock delayed data at SDO

All DAC Registers Preset to 80

H (Note 1)

Load Serial Register Data into DAC(X) Register

Note 1: "Preset" may not persist at all DACs if LOADH is high when PRESETL returns high.

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