292

of generating a programmable pseudoground

voltage at the V

very useful if any channels are to be used in AC–

multiplying applications. In such applications,

the pseudoground will set the DC offset of the

output signal. The voltage output of this circuit

as the code is decreased is non–linear because

the DAC bootstraps the increased output volt-

age by a larger fraction at each code. It is really

meant to be programmed only over a range of

codes between 104 and perhaps 60. It does

exhibit a fairly well–defined output, even if

non–intentional codes are programmed. For

codes above 112, the output stage resembles a

50 Ohm resistor to ground, and the V

will be near 1.3V, depending upon the loading at

the other V

output voltage will continue to rise until limited

by available current through R

R

must be chosen in order to supply enough cur-

rent for all channels, especially if any of the

other eight inputs are to be grounded. A plot of

V

all other inputs either grounded or tied to the

supply.

Figure 12 shows a programmable gain/attenua-

tor section using the programmable VREFL

drive. The VREFL of each DAC is actually

internally connected. When the optional 45

µF

noise reduction capacitor is included, this cir-

cuit is capable of 86dB of SNR and 74 to 84dB

of SINAD at 1kHz, depending on the pro-

Figure 12. AC–Coupled, Programmable Gain/Attenuator with Bootstrapped Programmable Output DC Offset (V

+

–

V

1/8 of SP9841

3

ICL8069

2kOhm

Load DACA with code 90; sets V

Then, load DACB with desired gain:

45µF*

301

Ω

1.22V

+

–

V

REFL

V

*(Optional Noise Reduction)

+5V

code 255 = +6dB

code 128 = 0dB

code 64 = –6dB

code

1 = –42dB

code

0 = –70dB

+

–

V

1/8 of SP9841

V

REFL

V

2.2µF

±0.75V