MIMXRT406LCFP4A datasheet(43/72 Pages) NXP

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Electrical characteristics

i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 3.1, 03/2022

NXP Semiconductors

Figure 22. FlexSPI output timing in DDR mode

4.6

Audio

This section provide information about SAI/I2S and SPDIF.

4.6.1

SAI/I2S switching specifications

This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.

All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]

= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock

and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal

(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

Table 39. Master mode SAI timing

Num

Characteristic

Min

Max

Unit

SAI_MCLK cycle time

2 x tsys

—

SAI_MCLK pulse width high/low

40%

60%

MCLK period

SAI_BCLK cycle time

4 x tsys

—

SAI_BCLK pulse width high/low

40%

60%

BCLK period

SAI_BCLK to SAI_FS output valid

—

SAI_BCLK to SAI_FS output invalid

—

SAI_BCLK to SAI_TXD valid

—

SAI_BCLK to SAI_TXD invalid

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

—

S10

SAI_RXD/SAI_FS input hold after SAI_BCLK

—

T CSS

T CK

TDVO

TDHO

TDVO

TDHO

TCSH

SCK

SIO[0:7]

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