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MIMXRT406LCFP4A Scheda tecnica(PDF) 54 Page - NXP Semiconductors |
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MIMXRT406LCFP4A Scheda tecnica(HTML) 54 Page - NXP Semiconductors |
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54 / 72 page ![]() i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 3.1, 03/2022 54 NXP Semiconductors Electrical characteristics s Figure 33. LPSPI Slave mode timing (CPHA = 0) Table 46. LPSPI Slave mode timing Number Symbol Description Min. Max. Units Note 1 fSCK Frequency of operation 0 fperiph / 2 Hz 1 1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be guaranteed this limit is not exceeded. 2 tSCK SCK period 2 x tperiph — ns 2 2 tperiph = 1 / fperiph 3 tLead Enable lead time 1 — tperiph — 4 tLag Enable lag time 1 — tperiph — 5 tWSCK Clock (SCK) high or low time tSCK / 2 - 5 — ns — 6 tSU Data setup time (inputs) 2.7 — ns — 7 tHI Data hold time (inputs) 3.8 — ns — 8 ta Slave access time — tperiph ns 3 3 Time to data active from high-impedance state 9 tdis Slave MISO disable time — tperiph ns 4 4 Hold time to high-impedance state 10 tV Data valid (after SCK edge) — 14.5 ns — 11 tHO Data hold time (outputs) 0 — ns — |
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